Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Reexamination Certificate
2006-04-25
2006-04-25
Phan, Trong (Department: 2827)
Static information storage and retrieval
Addressing
Particular decoder or driver circuit
C365S200000, C365S233100
Reexamination Certificate
active
07035163
ABSTRACT:
A decoder providing asynchronous reset, redundancy, or both. an asynchronously-resettable decoder with redundancy. The decoder has a synchronous portion, responsive to a clocked signal; an asynchronous portion coupled with an asynchronous circuit; a feedback-resetting portion, which substantially isolates the synchronous portion from the asynchronous portion coupled with, and interposed between the synchronous portion in response to a asynchronous reset signal; a signal input; a first memory output coupled with a first memory cell group; a second memory output coupled with a second memory cell group; and a selector coupled between the signal input, the first memory output, and the second memory output. This decoder can be memory row-oriented, and thus provide an asynchronously-resettable row decoder with row redundancy, or an asynchronously-resettable column decoder with column redundancy.
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Afghahi Morteza (Cyrus)
Terzioglu Esin
Broadcom Corporation
McAndrews Held & Malloy Ltd.
Phan Trong
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