Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons
Patent
1989-07-12
1990-11-13
Callahan, Timothy P.
Electrical transmission or interconnection systems
Nonlinear reactor systems
Parametrons
307279, 307291, 307452, H03K 3289, H03K 326, H03K 329
Patent
active
049704079
ABSTRACT:
A conventional D-type flip-flop transfers the data input D to a first output Q and a second output Q', where the second output Q' is the complement of the first output Q, on the transitions of a clock signal CK. This involves the transfer of data from a master latch and a series-connected slave latch which are loaded on alternating phases of the clock signal CK. The present invention provides for asynchronous loading of replacement data into the flip-flop by using a tri-stable buffer in both the master and slave latches. In response to a load signal LD, replacement data is injected into the master and slave latches overriding the current value stored at the Q and Q' outputs. This occurs because the load signal disables the normally active buffers while activating the loading buffers causing the normally active data path to go the tri-state condition. The state of the clock signal CK is of no importance to the outcome of the asynchronous load operation since both the master and the slave latch are overwritten during the load phase.
REFERENCES:
patent: 4394586 (1983-07-01), Morozumi
patent: 4485317 (1984-11-01), Davies, Jr.
patent: 4568842 (1986-02-01), Koike
Craig, "Hi Speed CMOS Latch Circuit", IBM Tech. Bulletin, vol. 27, No. 1B, Jun. 1984, pp. 663-664.
Callahan Timothy P.
National Semiconductor Corporation
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