Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
1999-09-21
2001-01-23
Nelms, David (Department: 2818)
Static information storage and retrieval
Addressing
Sync/clocking
C365S145000, C365S194000, C365S230010, C365S233500
Reexamination Certificate
active
06178138
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to integrated circuit devices and methods of operation thereof, and more particularly, to integrated circuit memory devices having clocked access cycles and methods of operation thereof.
2. Statement of the Problem
Integrated circuit memory devices are used to store information in a wide variety of electronic devices including, among others, personal computers, personal digital assistants, cellular radiotelephones and the like. For example, an integrated circuit memory device may be used to store data for retrieval and processing by a microprocessor or similar data processing device. To read data stored in a memory cell of a memory device, the microprocessor typically supplies an address to an address input of the integrated circuit device, e.g., drives an address bus to which the microprocessor and the memory device are connected, the signals applied to the address bus corresponding to the desired memory cell. In response, the memory device produces the data stored in the desired cell at an output port, e.g., drives a data bus connecting the memory and the microprocessor with signals corresponding to the data stored in the desired memory cell. As the design of microprocessor systems has advanced, the demands on memory devices have increased. In particular, higher processor speeds have led to demands for increased data throughput between memory devices and processors.
Many integrated circuit memory devices operate according to a clocked memory access cycle. For example, ferroelectric random access memory (FeRAM) devices typically operate according to an access cycle that is controlled by a memory clock signal which may be externally supplied or internally generated. After an externally supplied address is used to generate internal row and column addresses, the state of a ferroelectric memory element, e.g., a ferroelectric capacitor, is sensed, typically by measuring charge transfer from the ferroelectric element. The sensing operation may be destructive, e.g., the charge transfer may result in a change of the polarization state of the ferroelectric capacitor. Accordingly, the access cycle often includes a restore cycle in which the original polarization of the ferroelectric capacitor is restored. Synchronous memory devices, such as synchronous dynamic random access memory (SDRAM) devices and synchronous static random access memory (SSRAM) devices, may also use a clocked access cycle controlled by a memory clock signal.
In many nonvolatile and static memory applications, however, synchronous operation between a memory device and external devices may not be desirable. In such applications, a read cycle may be initiated simply by asserting a Chip Enable ({overscore (CE)}) signal and applying an address signal to a memory device's address input to access the addressed memory cell. In response, a signal corresponding to the contents of the addressed memory cell is asserted at an output port of the memory device within tens of nanoseconds of the address assertion. A new memory cell can be accessed by holding the signal constant and asserting a new address at the address input in a generally asynchronous manner.
Accordingly, in many memory applications it is desirable to access a memory device in an asynchronous manner, i.e., without requiring dependence on a common clock signal. Unfortunately, many memory devices that may be well suited for static memory applications, such as ferroelectric memory devices, are more desirably operated according to a clocked access cycle.
SUMMARY OF THE INVENTION
In light of the foregoing, it is an object of the invention to provide clocked integrated circuit memory devices and methods of operation therefor that can provide an asynchronous interface to external devices.
It is another object of the invention to provide ferroelectric integrated circuit memory devices and methods of operation that can provide an asynchronous interface to external devices.
A further object of the invention is to provide an asynchronously addressable clocked controller and methods of operation for such a controller.
These and other objects, features and advantages are provided according to the invention by integrated circuit memory devices and methods in which memory cells in a memory array are accessed by an asynchronously addressable clocked memory controller, i.e., a memory controller that receives address inputs asynchronously with respect to a memory clock signal that controls access to the memory array.
The invention provides an integrated circuit memory device comprising: an external signal input for receiving an externally supplied address signal; a timing circuit for providing a clock signal; a memory array including a plurality of memory cells; and an asynchronously addressable clocked memory controller communicating with the external signal input and the memory array and responsive to the timing circuit for receiving an externally supplied address asynchronously with respect to the memory clock signal and for accessing a selected memory cell associated with the address synchronously with respect to the memory clock signal. Preferably, the asynchronously addressable clocked memory controller comprises: a clocked memory control circuit responsive to the clock signal and communicating with the memory array for accessing the selected memory cell during an access cycle of the memory array; and an asynchronous address buffer circuit communicating with the input for receiving the address asynchronously with respect to the clock signal and communicating with the clocked memory control circuit to apply the address to the clocked memory control circuit. Preferably, the asynchronous address buffer circuit comprises: a first electronic storage element for storing a first one of the externally supplied addresses; and a second electronic storage element for storing a second one of the externally supplied addresses. Preferably, the first and second electronic storage elements comprise latches. Preferably, the asynchronous address buffer circuit comprises an address transition detector for providing an address detect signal upon receipt of the externally supplied address. Preferably, the asynchronous address buffer circuit comprises: an electronic storage element for storing the externally supplied address; an input switch between the input and the first electronic storage element; and the address transition detector applies the address detect signal to the input switch. Preferably, the asynchronous address buffer circuit further comprises: an output switch between the first electronic storage element and the clocked memory control circuit; and a memory access cycle timer responsive to the address detect signal for applying an address select signal to the output switch. Preferably, the asynchronous address buffer circuit further comprises: a first electronic storage element for storing a first externally supplied address and a second electronic storage element for storing a second externally supplied address; a first input switch between the input and the first electronic storage element and a second input switch between the input and the second electronic storage element; a first output switch between the first electronic storage element and the clocked memory control circuit; a second output switch between the second electronic storage element and the clocked memory control circuit; and the memory access cycle timer is responsive to a first address detect signal for applying a first address select signal to the first output switch and is responsive to a second address detect signal for applying a second address select signal to the second output switch. Preferably, a clocked memory control circuit accesses a first selected memory cell associated with the first address during a first access cycle of the memory array and accesses a second selected memory cell associated with the second address during a second access cycle of the memory array. Preferably, the clocked memory control circuit a
Cordoba Michael V.
Derbenwick Gary F.
Hirose Ryan T.
Kamp David A.
Celis Semiconductor Corporation
Duft, Graziano & Forest, P.C.
Ho Hoai V.
Nelms David
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