Electrical pulse counters – pulse dividers – or shift registers: c – Systems – Using particular code or particular counting sequence
Reexamination Certificate
2002-11-14
2004-05-11
Wambach, Margaret R. (Department: 2816)
Electrical pulse counters, pulse dividers, or shift registers: c
Systems
Using particular code or particular counting sequence
C377S045000, C377S104000, C377S107000, C377S126000
Reexamination Certificate
active
06735270
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to integrated circuit (IEC) devices. More particularly, the present invention relates to asynchronous counters and a method for operating the same.
BACKGROUND OF THE INVENTION
A high-speed, low power up-down counter is a fundamental component used in many applications, for example, statistics collections circuits, down-sampling circuits, and clock-data-recovery circuits in various communications channels. One conventional approach to achieve a high-speed counter is to partition a synchronous N-bit counter into multiple smaller counters (sub-counter blocks) in a pipeline fashion. Each sub-counter block is supplied with a clock signal which is gated by a control signal. Such a control signal is typically generated using an adjacent less-significant block so as to reduce power consumption. However, this approach requires more complex circuitry because of the gated clock overhead, and also consumes more power than asynchronous approach.
Another widely used conventional approach is to build an asynchronous (or ripple) counter, especially for applications in which latency is not an issue.
FIG. 1
schematically illustrates a conventional asynchronous counter
10
. As shown in
FIG. 1
, the Q output of a flip-flop at the n-th bit position is connected to the clock input of a flip-flop at the (n+1)-th bit position. Positive edge-triggered flip-flops are used for a down counter, and negative edge-triggered flip-flops are used for an up counter. Since operation speed is limited only by the toggling rate of the first-stage flip-flop, a very high speed can be achieved. However, the conventional asynchronous counters can only count in one direction.
Therefore, it would be desirable to provide a high-speed, low-power counter which can count in both directions.
BRIEF DESCRIPTION OF THE INVENTION
An asynchronous up-down counter includes a plurality of counter blocks. Each of the counter blocks has a counter output, an up-down control output, and an up-down control input. A counter signal output from each of the counter blocks has at least two bits. The asynchronous up-down counter also includes a signal bus coupling the up-down control output of a first counter block counting lesser significant bits to the up-down control input of a second counter block counting more significant bits. An up-down control signal output from each of the counter blocks has at least two bits. The up-down control signal may include a first control signal enabling counting operation of the second counter block and a second control signal indicating counting-up and counting-down.
REFERENCES:
patent: 4780894 (1988-10-01), Watkins et al.
LSI Logic Corporation
Thelen Reid & Priest LLP
Wambach Margaret R.
LandOfFree
Asynchronous up-down counter and method for operating the same does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Asynchronous up-down counter and method for operating the same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Asynchronous up-down counter and method for operating the same will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3211870