Asynchronous transfer mode system for, and method of,...

Multiplex communications – Pathfinding or routing – Switching a message which includes an address header

Reexamination Certificate

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Details

C370S412000

Reexamination Certificate

active

07009981

ABSTRACT:
A status queue in a host and a control queue in a segmentation and reassembly (SAR) subsystem are on opposite sides of a host bus in a control plane. Buffer descriptors in the host and the SAR and buffers in the host are in a data plane. To transfer cell payloads to a first line interfacing the SAR, the host writes the SAR that it has such cell payloads. The host writes the host buffer descriptors into the control queue to obtain the transfer of the buffer payload to the first line. The SAR writes the status queue when the transfer has been completed. To transfer cell payloads to the host memory, the host writes into the control queue the address of the buffers to receive the payload from the SAR. The SAR then writes the buffer descriptors to the status queue to obtain the transfer of the cell payloads to the buffers. Each of the control and status queues may be respectively considered to constitute two (2) control queues and two (2) status queues. The SAR determines if either status queue is full by comparing the address written by the SAR into such status queue with the address written by the host periodically to the SAR where the host is in the status queue. The host determines if either control queue is full by comparing the address written by the host into such control queue with the address written by the SAR periodically to the host where the SAR is in the control queue.

REFERENCES:
patent: 5796735 (1998-08-01), Miller et al.
patent: 0 551 191 (1993-07-01), None
patent: WO 96/08896 (1996-03-01), None
Tomimitsu, Yasuharu, “An ATM Chip Set for High Performance Computer Interfaces, Affording over 100 Mbps Sustained Throughput,” IEICE Transactions on Electronics, Dec. 1995, No. 12 Tokyo, JP.

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