Asynchronous transfer mode switch

Details Asynchronous transfer mode switch Asynchronous transfer mode switch

1998-11-09

2002-11-19

Yao, Kwang Bin (Department: 2664)

Multiplex communications

Pathfinding or routing

Through a circuit switch

C370S381000, C370S395100

Reexamination Certificate

active

06483831

ABSTRACT:

BACKGROUND
1. Field of the Invention
This invention pertains to switches, such as telecommunications switches, through which ATM cells are routed.
2. Related Art and Other Considerations
The increasing interest for high band services such as multimedia applications, video on demand, video telephone, and teleconferencing has motivated development of the Broadband Integrated Service Digital Network (B-ISDN). B-ISDN is based on a technology know as Asynchronous Transfer Mode (ATM), and offers considerable extension of telecommunications capabilities.
ATM is a packet-oriented transfer mode which uses asynchronous time division multiplexing techniques. Packets are called cells and traditionally have a fixed size. A traditional ATM cell comprises 53 octets, five of which form a header and forty eight of which constitute a “payload” or information portion of the cell. The header of the ATM cell includes two quantities which are used to identify a connection in an ATM network over which the cell is to travel, particularly the VPI (Virtual Path Identifier) and VCI (Virtual Channel Identifier). In general, the virtual is a principal path defined between two switching nodes of the network; the virtual channel is one specific connection on the respective principal path.
At its termination points, an ATM network is connected to terminal equipment, e.g., ATM network users. Typically between ATM network termination points there are plural switching nodes, the switching nodes having ports which are connected together by physical transmission paths or links. Thus, in traveling from an originating terminal equipment to a destination terminal equipment, ATM cells forming a message may travel through several switching nodes.
A switching node has a plurality of ports, each of which can be connected by via a link circuit and a link to another node. The link circuit performs packaging of the cells according to the particular protocol in use on the link. A cell incoming to a switching node may enter the switching node at a first port and exit from a second port via a link circuit onto a link connected to another node. Each link can carry cells for plural connections, a connection being e.g., a transmission between a calling subscriber or party and a called subscriber or party.
The switching nodes each typically have several functional parts, a primary of which is a switch core. The switch core essentially functions like a cross-connect between ports of the switch. Paths internal to the switch core are selectively controlled so that particular ports of the switch are connected together to allow a message ultimately to travel from an ingress side of the switch to an egress side of the switch, and ultimately from the originating terminal equipment to the destination terminal equipment.
U.S. Pat. No. 5,467,347 to Petersen discloses an ATM switch in which various types of ATM cells, all of essentially uniform length, are transmitted between a switch core and ports of the switch. The types of cells include traffic cells, operation and maintenance cells, and idle cells. Although all types of cells have essentially the same length, not all cells are necessarily full, thus causing some loss in transmission efficiency. The traffic cells are fed from originating switch ports to buffers at cross points of the switch matrix, and then are unloaded from the buffers to destination or target switch ports. The traffic cells sent from the originating switch ports to the switch have a relay address field in which each bit corresponds to a target switch port. Traffic cells unloaded from the switch core and sent to the target switch ports each have a relay poll field which indicate which target switch ports are occupied and which are free. Thus, each traffic cell is encumbered with information reflecting status of switch ports.
What is needed, therefore, and an object of the present invention, is an efficient ATM switching system which judiciously formats and utilizes ATM cells of differing types.
SUMMARY
An asynchronous transfer mode (ATM) switch has plural switch ports connected by respective bidirectional links to a switch core. The switch core includes a memory array unit which comprises two buffer matrices of cross point units. Connected to each switch port is a corresponding row column unit, each row column unit managing the writing of service cells to one row of cross point units and the reading of service cells from one column of cross point units.
The bidirectional links between each switch port and its corresponding row column unit of the switch core carry both service cells and control cells. The service cells, also known as traffic cells or information cells, obtained at an incoming or originating switch port, are routed through the switch core to an outgoing or destination switch port. The control cells do not contain switched information, but instead are dedicated for carrying information used for management and operation of the switching system.
The ATM switching system of the present invention allows cells of differing sizes to be carried on the bidirectional links between its switch core and its switch ports. For example, the service cells have a differing cell size than the control cells, and the cell size of the service cells need not necessarily be uniform.
Service cells can be of differing cell size such that two successive service cells need not have the same length or same size of payload. The service cells transmitted on the bidirectional length include a cell size field, the cell size field indicating the cell size of the each service cell in which it is included. In an example embodiment, service cells can be of any of the following cell sizes (in bytes): 8, 16, 24, 32, 40, 48, and 56.
By contrast, control cells utilized in the exemplary embodiment each are four bytes in length. Differing types of control cells (e.g., LCC-cells and LSC-cells) are provided, with each control cell type having a differing format. The LCC control cells are known as link connection control cells; the LSC control cells are known as link synchronization control cells.
Both the switch port and its corresponding row column unit in the switch core have synchronization state machines which exchange LSC control cells. The LSC control cells include information for synchronizing operation of the two state machines. In particular, the LSC control cells have a format which includes a field indicative of one of a plurality of synchronization states of the machine which generated the LSC control cell. By employing short, synchronization-dedicated LSC control cells in a pre-established protocol, synchronization of switch port and switch core are economically and quickly achieved and maintained.
Each row column unit includes a set of control registers as part of its cross point status unit. The set of control registers is distinct from the buffers of the cross point unit through which service cells are switched. Each switch port can control, at least in part, its associated row column unit of the switch core by writing and reading non-service information, e.g., control information, to and from the set of control registers.
Some of the control registers are known as “bitmapped” registers since each bit of such control register is associated to one of the plural switch ports connected to the switch core. Among the bitmapped control registers are the pollstate_status registers and the pollstate_release registers. A given row column unit has the bits of its pollstate_status register set to indicate whether cross point buffers in its same row of the core matrix are “occupied” or “free”. The pollstate_release register of the row column unit has bits set to indicate whether the buffers in the row managed thereby have transitioned from “occupied” to “free” or whether the buffers have not transitioned.
Various ones of the control registers are employed, e.g., to establish various operating parameters of the switching system. Such parameters can include, for example, certain sequences of operation (e.g., poll enable, scan enable), certain ti

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