Multiplex communications – Data flow congestion prevention or control – Control of data admission to the network
Reexamination Certificate
2000-02-01
2004-03-23
Hsu, Alpus H. (Department: 2665)
Multiplex communications
Data flow congestion prevention or control
Control of data admission to the network
C370S395400
Reexamination Certificate
active
06711130
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to an asynchronous transfer mode data communication technology and, more particularly, to an asynchronous transfer mode data transmitting apparatus scheduled in an allowed cell rate and a method used therein.
DESCRIPTION OF THE RELATED ART
An asynchronous transfer mode, which is hereinbelow abbreviated as “ATM”, communication has service classes, one of which is called as “available bit rate”. When the ATM data communication is controlled under the available bit rate, pieces of input data information are stored in a content addressable memory, and the pieces of data information stored in the content addressable memory are scheduled for data transmission at an optimum transmission rate in the feedback control of congestion status.
It is difficult to apply a hardware and a software designed in the constant bit rate to a data communication in the available bit rate. Japanese Patent Publication of Unexamined Application (laid-open) No. 8-242238 discloses a communication control unit for the ATM data communication, which is applicable to the data communication in the available bit rate. The content addressable memory is incorporated in the prior art communication control unit for scheduling the data transmission. The prior art ATM communication system comprises plural ATM switching units, an ATM server, ATM terminals and an ATM network connected thereto. The prior art communication control unit serves as the ATM server or the ATM terminal.
The ATM communication control unit includes a system bus, which is connected to a system memory for storing transmission data, a host computer and a transmitter-receiver. The transmitter-receiver is connected through a physical device to the ATM network, and is further connected to a control memory. The host computer contains a CPU (Central Processing Unit), and the transmitter-receiver includes a receiving section and a transmitting section both connected through the physical device to the ATM network. The transmitter-receiver further includes a host interface connected to the system bus and a control memory interface connected to the control memory.
FIG. 1
shows a part of the transmitting section of the above-described transmitter-receiver disclosed in the Japanese Patent Publication of Unexamined Application. The prior art transmitting section includes a transmitting controller
40
, and the transmission controller
40
is associated with a counter
50
and a content addressable memory section
51
. The transmission controller
40
cooperates with the counter
50
and the content addressable memory section
51
, and varies the transmission timings depending upon the peak rates of the virtual channels VC. The content addressable memory section
51
includes plural content addressable memory cell arrays
511
. When an interrogative data pattern is supplied to the content addressable memory cell arrays
511
, the content addressable memory cell arrays
511
compares the interrogative data pattern with stored bit strings to see whether or not any stored bit string is matched with interrogative data pattern. When the content addressable memory cell arrays
511
find a stored bit string matched with the interrogative data pattern, the content addressable memory cell arrays output the address assigned to the memory location where the bit string is stored. The addresses arc corresponding to the virtual channels VC, respectively, and a data code stored in each memory location is representative of a time to transmit the next cell to each virtual channel.
The content addressable memory cell arrays
511
are associated with an address decoder
512
, a collation register
513
and a selector
516
. The transmission controller
40
and the counter
50
are connected to the selector
516
, and the selector
516
selectively connects the transmission controller
40
and the counter
50
to the content addressable memory cell arrays
511
under the control of a mode changer
515
. The transmission controller
40
instructs the mode changer
515
how to control the selector
516
. The collation register
513
is connected through a priority encoder
514
to the transmission controller
40
.
The counter
50
increments the stored value at time intervals each equal to a time period required for transmission of a single cell. The stored value is continuously incremented, and, accordingly, is representative of time.
The transmission controller
40
supplies a mode signal to the mode changer
515
, and the mode signal is indicative of the write-in mode or the retrieval mode. The mode signal is assumed to indicate the write-in mode. The mode changer
515
controls the selector
516
in such a manner as to connect the transmission controller
40
to the content addressable memory cell arrays
511
, and supplies an address signal representative of the memory location corresponding to one of the virtual channels VC. The transmission controller
40
supplies a data code representative of a time (Tp+Ts) to transmit a cell through the selected virtual channel VC through the selector
516
to the content addressable memory cell arrays
511
. Then, the data code is stored in the memory location corresponding to the selected virtual channel VC. In this way, data codes are written into the memory locations corresponding to the virtual channels VC.
The transmission controller
40
checks the content addressable memory cell arrays
511
to see whether or not the ATM communication control unit has to transmit a cell through any channel. The transmission controller
40
supplies the mode signal representative of the retrieval mode to the mode changer
515
, and causes the selector
516
to connect the counter
50
to the content addressable memory cell arrays
511
. The bit pattern representative of the stored value or the present time is supplied through the selector
516
to the content addressable memory cell arrays
511
as the interrogative data pattern. The content addressable memory cell arrays
511
compares the bit pattern with the data codes respectively stored in the memory locations to see whether or not the time to transmit a cell comes. If a data code or data codes are consistent with the bit pattern, logic “1” is written into a memory cell or memory cells of the collation register
513
corresponding to the memory location or the memory locations where the data code or the data codes are stored. If plural data codes are matched with the data pattern, logic “1” is written into the corresponding memory cells, and the priority encoder
514
prioritizes the virtual channels VC, and the address corresponding to the highest priority is transferred to the transmission controller
40
.
Japanese Patent Publication of Unexamined Application No. 10-56492 discloses another prior art communication controlling apparatus.
FIG. 2
shows the prior art communication controlling apparatus disclosed in the Japanese Patent Publication of Unexamined Application. The prior art communication controlling apparatus comprises a data transmission controller
2
connected to a transmission rate controller
23
and a PCI bus
7
, a transmitter
5
connected between the transmission data controller
2
and a cable
13
and a system memory
4
connected to the PCI bus
7
. The transmission rate controller
23
manages the timings to transmit cells through plural virtual channels VC.
The transmission rate controller
23
includes a content addressable memory array
25
. Plural memory locations arc defined in the content addressable memory array
8
, and each of the memory locations has an address field
8
and a data field
19
. The data field
19
is divided into a data sub-field
21
assigned to a time to transmit a cell and another sub-field
17
assigned to a priority flag. The content addressable memory array
25
is associated with a collation register
27
, where results of comparison are stored. A selector
24
is connected between the content addressable memory array
25
and the data transmission controller
2
, and selectively transfe
Foley & Lardner
Hsu Alpus H.
NEC Electronics Corporation
LandOfFree
Asynchronous transfer mode data transmitting apparatus and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Asynchronous transfer mode data transmitting apparatus and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Asynchronous transfer mode data transmitting apparatus and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3278700