Asynchronous transfer mode data cell routing device for a revers

Details Asynchronous transfer mode data cell routing device for a revers Asynchronous transfer mode data cell routing device for a revers

1995-06-19

1996-08-13

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

370 941, H04L 1256

Patent

active

055463932

ABSTRACT:
A routing bits generator is associated with one or more reverse Omega networks with L stages and 2.sup.N inputs. 2.sup.N state bits, indicating whether the cells to be routed are free or occupied, are loaded in parallel into a state register, then shifted in series in this register. The state bits delivered successively by the serial output of the state register, filtered if L<N, serve to increment a first counter or decrement a second counter depending on the values of the state bits, and to select one or the other of the two counters at the input of a multiplexer. L addressing registers, receiving in serial shift mode the L address bits provided by the multiplexer, are cascaded in such a way that after 2.sup.N serial shift cycles, their contents can be transferred in parallel to means inserting the address bits at the head of the cells.

REFERENCES:
patent: 4365292 (1982-12-01), Barnes et al.
patent: 5287346 (1994-02-01), Bianchini et al.
patent: 5287491 (1994-02-01), Hsu
patent: 5299317 (1994-03-01), Chen et al.
patent: 5440549 (1995-08-01), Min et al.

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