Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
Reexamination Certificate
1998-06-22
2001-10-23
Hsu, Alpus H. (Department: 2662)
Multiplex communications
Pathfinding or routing
Switching a message which includes an address header
C370S401000, C370S463000, C370S469000, C709S230000, C709S250000
Reexamination Certificate
active
06307857
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to data communications architecture and, more particularly, to asynchronous transfer mode (ATM) communication control apparatus for performing processing of low-level or infrastructure part of ATM protocols. The invention also relates to ATM controllers adaptable for use with the communication control apparatus in executing internal processing tasks thereof as well as control methods implementable therein.
ATM communication control apparatus is implemented and practiced for interconnection of a plurality of terminal units and communication lines of an ATM network operatively associated therewith to permit execution of communications between terminals pursuant to a preselected ATM protocol. More practically, an ATM communication control device is designed to execute processing at the infrastructure part of the ATM protocol in a way such that upon receipt of one or more variable length packets of information as generated at terminals, the controller divides each packet into a plurality of fixed length cells which are then transmitted to a communication line while simultaneously receiving cells from the line to generate one or more packets which are then passed to its intended terminal. Note that standardization of the ATM protocol per se is now in progress by the ATM Forum based on the recommendation of International Telecommunication Union (ITU).
One ATM controller is implemented using a large-scale integrated circuit (LSI) chip set which is designed to perform certain part of the processing tasks of the ATM communication control device, which may involve the processing of an ATM layer for cell transmit/receive operations and processing of an ATM adaptation layer (AAL) for subdivision and assembly of cells, namely, slicing and reconstruction, or alternatively, “segmentation” and “reassembly.” A combination of such ATM layer processing and AAL layer processing will be referred to as the “ATM protocol processing” hereinafter. One example of such ATM controller may be the LSI microcomputer model &mgr;PD98401/&mgr;PD98402 used for ATM-LAN which has been disclosed in NEC Technical Bulletin Vol. 47, No. 7, 1994. This controller is designed to employ hard wired logic circuits that execute the ATM protocol processing through fixed or non-modifiable procedure routines. This architecture disclosed is capable of increasing performance. Unfortunately, this does not come without accompanying a penalty: functional inflexibility, that is, an inability to permit any change or alteration in content of processing once determined. The presently available ATM protocol is such that some processing parts still remain unstandardized, including the processing of administrative or “system management” cells which may be operation, administration and maintenance cells, these are collectively called the “OAM” cells among those skilled in the art, for use in routine maintenance and handling operations, plus resource management (RM) cells for use in controlling the congestion of traffic over communication links. It is desirable that ATM controllers be capable of accommodating any possible changes and alterations of such parts unstandardized.
One exemplary ATM controller capable of accommodating the need for processing alterations is the device called “ATMizer” which has been disclosed in a Japanese publication “NIKKEI Electronics”, August 1994 at pages 1-4. This ATM controller disclosed comes with a built-in microprocessor for execution of software-based processing tasks to handle many parts of the ATM protocol processing, including cell header analysis, cell segmentation/reassembly processes and others.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide an ATM control apparatus with a reduced capacity memory for use in subdividing and/or assembling data cells concerned.
It is another object of the invention to provide an ATM controller device capable of accommodating various setup configurations and alterations of protocol processing while reducing loads on the software-based processing required.
To attain the foregoing objects the present invention provides a specific ATM controller adapted for performing processing tasks of the ATM layer and AAL layer of a selected ATM protocol between data transfer paths of an ATM network and one or more terminals. Each terminal includes a built-in memory device whereas the ATM controller has its buffer memory. This ATM controller includes a transfer circuit which is operatively connected to the buffer memory and which is responsive to receipt of packets of data sent from a terminal for transferring the data packets between the built-in memory of the terminal and the buffer memory with a shorter predetermined length data block being a unit. The controller also includes a cell transmit control circuit which is operable, upon transmission of data blocks from the terminal memory toward the buffer memory, to subdivide or slice such data blocks into data cells which are then sent forth to the ATM network side. A cell receive control circuit is operatively coupled to the buffer memory for reconstructing or reassembling the received data cells into a predetermined length data block in the storage space of the buffer memory. A transfer control circuit is provided which is responsive to completion of a transmit/receive attempt of those data cells corresponding to one data block for generating and issuing a transfer instruction that permits the transfer circuit to effectuate the intended data transfer.
One significant advantage of the ATM controller lies in capability to employ a buffer memory with reduced storage capacity and cost. This can be said because the controller is specifically configured to achieve the data packet transmission between the terminal memory and the buffer memory with a predetermined length data block being used a unit while allowing this transmission to be done every time when those data cells corresponding to one data block are transmitted or received, which may in turn permit the buffer memory to have a reduced storage space for use in storing a mere single data block per ATM connection, any extra memory capacity is no longer required.
In accordance with another aspect of the instant invention, an ATM controller is provided which is similar in configuration to the ATM controller stated supra and which is featured by including a cell type identifier circuit and a rewritable program storage memory device as well as a microprocessor operatively associated therewith. The cell type identifier attempts to analyze the header section of a cell as presently received from the ATM network side to thereby determine or “judge” whether this cell is a data cell or not. The program memory may be an electrically erasable programmable semiconductor memory device that is arranged to and hold store therein control software programs. The microprocessor is for execution of processing tasks including, but not limited to, analysis of those cells other than the data cells as identified during the “judgment” procedure, and also certain processing tasks as required in conformity with such analysis results.
An advantage of this arrangement is that the ATM controller may successfully accommodate or “absorb” a variety of setup configurations and any possible alterations of the ATM protocol processing as assigned to the microprocessor. Another advantage lies in a decrease in load on the software processing because of the fact that the microprocessor is without the need to perform the cell type judgment tasks and data cell slicing/reconstruction or segmentation/reassembly tasks.
These and other objects, features and advantages of the invention will be apparent from the following more particular description of preferred embodiments of the invention, as illustrated in the accompanying drawings.
REFERENCES:
patent: 4539678 (1985-09-01), Ambroise et al.
patent: 5414707 (1995-05-01), Johnson et al.
patent: 5548587 (1996-08-01), Bailey et al.
patent: 5606559 (1997-02-01), Badger et al.
patent:
Hashi Eizo
Mizutani Mika
Takada Osamu
Yokoyama Tatsuya
Antonelli Terry Stout & Kraus LLP
Hitachi , Ltd.
Hsu Alpus H.
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