Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
Patent
1996-05-09
1998-05-05
Hsu, Alpus H.
Multiplex communications
Pathfinding or routing
Switching a message which includes an address header
370428, 395566, H04L 1256
Patent
active
057486301
ABSTRACT:
Methods and apparatus for processing cells in an asynchronous transfer mode (ATM) communication system. An ATM cell processor includes a load multiple instruction which provides a burst transfer of a data block from an external control memory, and allows the result of a subsequent operation on a loaded value to be automatically written back to the control memory location from which it was previously read. The instruction may specify the address in the control memory of a data block to be retrieved, a destination register in a CPU register file into which the first retrieved halfword of a data block will be loaded, and a total number of halfwords to be retrieved. The instruction includes a link field option which directs the storage of information linking the processor registers which receive the retrieved halfwords to the control memory locations from which the halfwords were read. An automatic memory update feature may be provided in an arithmetic logic unit (ALU) instruction which operates on one or more of the processor registers receiving the halfwords retrieved by the instruction, such that the result of the corresponding ALU operation will be automatically written back to the control memory location or locations which supplied one or more of the operands.
REFERENCES:
patent: 4589087 (1986-05-01), Auslander et al.
patent: 4926374 (1990-05-01), Schaffer
patent: 5008807 (1991-04-01), Kruger et al.
patent: 5130975 (1992-07-01), Akata
patent: 5241536 (1993-08-01), Grimble et al.
patent: 5247627 (1993-09-01), Murakami et al.
patent: 5253247 (1993-10-01), Hirose et al.
patent: 5265091 (1993-11-01), van Landegem
patent: 5271005 (1993-12-01), Takase et al.
patent: 5274641 (1993-12-01), Shobatake et al.
patent: 5280475 (1994-01-01), Yanagi et al.
patent: 5365519 (1994-11-01), Kozaki et al.
patent: 5379295 (1995-01-01), Yonehara
patent: 5381407 (1995-01-01), Chao
patent: 5394397 (1995-02-01), Yanagi et al.
patent: 5420859 (1995-05-01), Takase et al.
patent: 5446726 (1995-08-01), Rostoker et al.
patent: 5448567 (1995-09-01), Dighe et al.
patent: 5450400 (1995-09-01), Denissen et al.
patent: 5455826 (1995-10-01), Ozveren et al.
patent: 5463622 (1995-10-01), Keller et al.
patent: 5467347 (1995-11-01), Petersen
patent: 5500851 (1996-03-01), Kozaki et al.
patent: 5521915 (1996-05-01), Dieudonne et al.
patent: 5526352 (1996-06-01), Min et al.
patent: 5530806 (1996-06-01), Condon et al.
patent: 5533020 (1996-07-01), Byrn et al.
patent: 5535201 (1996-07-01), Zheng
patent: 5541918 (1996-07-01), Ganmukhi et al.
patent: 5548588 (1996-08-01), Ganmukhi et al.
patent: 5577035 (1996-11-01), Hayter et al.
patent: 5598410 (1997-01-01), Stone
patent: 5598541 (1997-01-01), Malladi
patent: 5610914 (1997-03-01), Yamada
Unpublished document, "CellMaker/SwitchMaker," Rev 0.2, Maker Communications Equipment Corp., Released under Non-disclosure Agreement, Feb. 22, 1995.
William Stallings, Local and Metropolitan Area Networks, Macmillan Publishing Corp., (New York, N.Y. 1993) pp. 260-261.
Bergantino Paul V.
Lussier Daniel J.
Hsu Alpus H.
Maker Communications, Inc.
Yao Kwang B.
LandOfFree
Asynchronous transfer mode cell processing system with load mult does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Asynchronous transfer mode cell processing system with load mult, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Asynchronous transfer mode cell processing system with load mult will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-63211