Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
Reexamination Certificate
1999-12-01
2004-11-23
Kizou, Hassan (Department: 2662)
Multiplex communications
Pathfinding or routing
Switching a message which includes an address header
C370S395600, C370S413000, C370S527000, C370S529000
Reexamination Certificate
active
06822960
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates generally to the field of telecommunications, and more particularly to an asynchronous transfer mode (ATM) switch and method for a telecommunications node.
BACKGROUND OF THE INVENTION
The Internet has dramatically increased the potential for data, voice, and video services for customers. Existing circuit-switched telephony systems, however, do not provide the foundation to support the growing need for bandwidth and new services required by both residential and business consumers. As a result, integrated access devices have been introduced to support Internet and related technologies as well as standard telephony service.
Integrated access devices often employ asynchronous transfer mode (ATM) functionality to multiplex data, voice and video traffic together onto a single network. ATM is a connection-oriented packet-switching technology in which information is organized into small, fixed length cells. ATM carries data asynchronously, automatically assigning data cells to available time slots on demand to provide maximum throughput. Compared with other network technologies, ATM provides large increases in maximum supported bandwidth, support for multiple types of traffic such as data, video, and voice transmissions on shared communication lines, and virtual networking capabilities, which increase bandwidth utilization and ease network administration.
Integrated access devices are typically implemented in a card shelf configuration with functionality of the device distributed between discrete line and switch cards connected over a backplane. The line cards provide the service interfaces for the different traffic types and segment and reassemble (SAR) time division multiplex (TDM) traffic to and from the ATM format. Traditional segmenting and reassembling functionality is processor intensive as it must account for channel associated signaling (CAS) values and other superframe information transmitted with TDM traffic. Implementing the SAR functionality on the line cards is expensive as the appropriate circuits must be included on each line card. Moving the SAR functionality to a central switch processor can interfere with normal traffic flows and processor upgrades to handle such additional processing can be prohibitively expensive for many low-cost applications in which access devices are utilized.
In addition to SAR functionality traffic, line cards in an integrated access device must also support inverse multiplexing of ATM (IMA). IMA provides an aggregate bandwidth capacity greater than a single T1 link, but less than a DS-3 link, by carrying a single ATM stream over multiple T1 links. To prevent cells in the stream from being misordered as they are transported over different links having different cell rates, latencies, and/or jitter, the IMA standard uses existing T1 UNI standards for IMA support. In particular, overhead cells are regularly transmitted that indicate the overall order pattern of the cells transported over the different links. This provides an intricate payload block mapping scheme that further increases processor requirements and costs of the line cards.
SUMMARY OF THE INVENTION
The present invention provides an improved asynchronous transfer mode (ATM) switch and method for a telecommunications node that substantially eliminate or reduce the disadvantages and problems associated with previous systems and methods. In particular, superframe and other extra-cell control information is carried in-band and the cell traffic is segmented and reassembled, reordered, and switched by a multiple purpose ATM switch.
In accordance with one embodiment of the present invention, an ATM switch includes a switch memory having a plurality of discrete queues. A queue is dedicated to a connection in which a traffic stream is transmitted in cells in an inverse multiplex ATM (IMA) format. A switch controller is operable to receive a plurality of cells, to identify cells for the connection, to queue cells for the connection in the queue based on order information received with the cells, to reconstitute from the queue the traffic stream and to switch the traffic stream.
More specifically, in accordance with a particular embodiment of the present invention, a second queue is dedicated to a second connection in which traffic is transmitted in ATM adaption layer (AAL) cells. In this embodiment, the switch controller is operable to identify AAL cells for the second connection, to store AAL cells for the second connection in the second queue based on order information received with each AAL cell, to reassemble from the second queue traffic transported in the AAL cells and to switch the reassembled traffic. The switch controller is further operable to identify ATM cells, to queue the ATM cells in one or more queues in the switch memory and to switch the ATM cells.
Technical advantages of the present invention include providing an improved ATM switch for a telecommunications node. In particular, an ATM switch segments and reassembles (SAR), reorders, and switches ATM traffic. As a result, SAR and IAM functionality and circuitry are offloaded from the line cards to the switch core. Thus, board space on the line cards and cost of the line cards are reduced.
Another technical advantage of the present invention includes providing a multiple purpose ATM switch. In particular, the multiple purpose ATM switch includes a shared memory and a common switch controller that queues traffic based on its type. As a result, the ATM switch comprises a single circuit that incorporates ATM switching, SAR functionality and IMA processing in one block of logic and memory. This provides implementation compactness and associated cost savings as well as a richer feature set within a single ATM switch card.
Still another technical advantage of the present invention includes providing an improved method and system for processing IMA traffic. In particular, an order indicator is included with every cell in an IMA stream. This order indicator is used to reorder the cells after they are transported and received over multiple T1 links. As a result, overhead cells need not be transmitted or processed by source and destination nodes which reduces processing requirements and optimizes bandwidth usage over a network.
Other technical advantages of the present invention will be readily apparent to one skilled in the art from the following figures, description, and claims.
REFERENCES:
patent: 4862451 (1989-08-01), Closs et al.
patent: 5457684 (1995-10-01), Bharucha et al.
patent: 5570362 (1996-10-01), Nishimura
patent: 5577039 (1996-11-01), Won et al.
patent: 5604742 (1997-02-01), Colmant et al.
patent: 5615211 (1997-03-01), Santore et al.
patent: 5734653 (1998-03-01), Hiraiwa et al.
patent: 5841771 (1998-11-01), Irwin et al.
patent: 5848067 (1998-12-01), Osawa et al.
patent: 5875192 (1999-02-01), Cam et al.
patent: 5943339 (1999-08-01), Mauger
patent: 5953330 (1999-09-01), Canniff et al.
patent: 6005865 (1999-12-01), Lewis et al.
patent: 6084880 (2000-07-01), Bailey et al.
patent: 6137795 (2000-10-01), Tominaga et al.
patent: 6167062 (2000-12-01), Hershey et al.
patent: 6222858 (2001-04-01), Counterman
patent: 6243382 (2001-06-01), O'Neill et al.
patent: 6314103 (2001-11-01), Medhat et al.
patent: 6404782 (2002-06-01), Berenbaum et al.
patent: 6442167 (2002-08-01), Aramaki et al.
patent: 6574221 (2003-06-01), Petersen
patent: 2002/0181484 (2002-12-01), Aimoto
patent: 0818941 (1998-01-01), None
ITU-T Recommendation I.363, “B-ISDN ATM Adaption Layer (AAL) Specification,” Mar. 1993, 100 pages.
Bellcore GR-253-CORE, “Synchronous Optical Network (SONET) Transport Systems: Common Generic Criteria,” Issue 2, Dec. 1995 (with rev. Jan. 1999), 788 pages.
ATM Forum, “Circuit Emulation Service Interoperability Specification,” Version 2.0, Jan. 1997, AF-VTOA-0078.000, 101 pages.
ATM Forum, “Specifications of (DBCES) Dynamic Bandwidth Utilization—in 64Kbps Time Slot Trunking over ATM—Using CES,” Jul. 1997, AF-VTOA-0085.000, 32 pages.
Bellcore GR-2837, “ATM Virtual Path Ring Fu
Buckland Kenneth M.
Dorbolo Riccardo G.
Field Barry W.
Manchester Earl B.
Baker & Botts L.L.P.
Cisco Technology Inc.
Kizou Hassan
Odland David
LandOfFree
Asynchronous transfer mode (ATM) switch and method does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Asynchronous transfer mode (ATM) switch and method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Asynchronous transfer mode (ATM) switch and method will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3308027