Asynchronous transfer mode (ATM) payload synchronizer

Multiplex communications – Wide area network – Packet switching

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370102, 370108, H04L 700

Patent

active

053847741

ABSTRACT:
The requirement of a separate payload clock in an ATM system is eliminated by increasing the number of bytes in an ATM cell and controllably generating and inserting idle cells so that a clock rate equal to that of the incoming SDH, SONET or the like clock rate may be used as a read clock. In one embodiment, the number of cells in a predetermined interval, for example 125 .mu.sec., is adjusted to be a predetermined integer number by inserting idle cells. This, in turn, allows the use of a "standard" available clock to delineate cell boundaries.

REFERENCES:
patent: 4688215 (1987-08-01), Fryer
patent: 4807221 (1989-02-01), Stummer
patent: 4833673 (1989-05-01), Chao et al.
patent: 5131012 (1992-07-01), Dravida
patent: 5214643 (1993-05-01), Mueller et al.
patent: 5274680 (1993-12-01), Sorton et al.
CCITT Recommendation I.432, "B-ISDN User-Network Interface-Physical Layer Specification", Geneva 1991.
CCITT Recommendation G.708, "Network Node Interface for the Synchronous Digital Hierarchy", Melbourne 1988.
CCITT Recommendation G.709, "Fascicle III.4-Rec. G.709", Melbourne 1988.
CCITT Recommendation I.361 (revised), "B-ISDN ATM Layer Specification" Jul. 1992.

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