Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
Reexamination Certificate
1999-03-16
2004-02-17
Chin, Wellington (Department: 2664)
Multiplex communications
Pathfinding or routing
Switching a message which includes an address header
C370S395510
Reexamination Certificate
active
06693911
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to an asynchronous transfer mode (ATM) apparatus which multiplexes and demultiplexes ATM cells, and more particularly to an ATM apparatus configured so that a plurality of ATM apparatuses which send and receive ATM cells through a Level 2 UTOPIA interface are connected in a hierarchical formation.
The ATM Forum Technical Committee proposes the Level 2 UTOPIA interface (UTOPIA)is an abbreviation of the Universal Test & Operations PHY Interface for ATM. The Level 2 UTOPIA interface prescribes an interface between an ATM layer device and a PHY (physical) layer device. More particularly, the Level 2 UTOPIA interface defines a single-stage structure in which a plurality of PHY layer devices are connected to a single ATM layer device. The maximum number of PHY layer devices connectable to the ATM layer device is equal to eight for 155 Mbps, and four for 622 Mbps. Hence, only a limited number of subscribers connected to the PHY layer devices can be accommodated in the single-stage structure.
2. Description of the Related Art
FIGS. 1 and 2
show a network system equipped with an ATM apparatus which performs multiplexing and demultiplexing of ATM cells. Referring to
FIG. 1
, the system includes in-house devices
13
-
1
of subscribers #
1
-#N, terminal devices
13
-
11
, network terminals
13
-
12
, and an office station
13
-
2
. The office station
13
-
2
includes an ATM switch
13
-
21
, an access network device
13
-
22
, and an operation system part (OPS)
13
-
2
. Referring to
FIG. 2
, a cabinet
14
-
1
is connected to the office station
13
-
2
, which includes the ATM switch
13
-
21
. The cabinet
14
-
1
includes an access network device
14
-
11
and an operating system part
14
-
12
.
The network system shown in
FIGS. 1 and 2
is a network system which employs an asymmetrical digital subscriber line (abbreviated as ADSL) transmission system. The ADSL transmission system is promising as a transmission system capable of sending data to the subscribers at high speed, such as digital communications through the Internet.
The access network devices
13
-
22
and
14
-
11
receive data received via the asymmetrical digital subscriber lines from the terminal devices
13
-
11
in the subscriber houses, and multiplex the received data in a cell multiplexing fashion. Then, the access network devices
13
-
22
and
14
-
11
send the cell-multiplexed data to the ATM switch
13
-
21
via an optical fiber. Further, the access network devices
13
-
22
and
14
-
11
demultiplex cell-multiplexed data transmitted from the ATM switch
13
-
21
via the optical fiber, and distribute demultiplexed data to the subscriber terminals
13
-
1
via the asymmetrical digital subscriber lines. Hence, the access network devices
13
-
22
and
14
-
11
are ATM apparatuses that perform ATM cell processes such as multiplexing and demultiplexing of a large number of ATM cells.
FIG. 3
illustrates a structure of the access network device
13
-
22
or
14
-
11
. The access network device includes asymmetrical digital subscriber line (ADSL) packages (cards)
15
-
1
, a control package
15
-
2
and a
155
Mbps interface package
15
-
3
. Each of the ADSL packages
15
-
1
is made up of asymmetrical digital subscriber line terminating devices (ATU-C)
15
-
11
, and a cell multiplexing/demultiplexing device
15
-
12
. The control package
15
-
2
includes a cell multiplexing/demultiplexing device
15
-
21
, an ATM switch chip
15
-
22
, a central processing unit (CPU)
15
-
23
, an Ethernet interface part
15
-
24
, and a cell multiplexing/demultiplexing device
15
-
25
. The ATM switch chip
15
-
22
includes a routing table
15
-
221
. The
155
Mbps interface package
15
-
3
includes an SDH terminating part (STM-
1
)
15
-
31
and an optical module
15
-
32
.
In each of the ADSL packages
15
-
1
, the cell multiplexing/demultiplexing device
15
-
12
respectively send data received from the asymmetrical digital subscriber lines to the cell multiplexing/demultiplexing device
15
-
12
, which multiplexes the received data in the cell multiplexing formation. Then, the cell-multiplexed data is output to the control package
15
-
2
. Cell-multiplexed data output from the control package
15
-
2
is demultiplexed by the cell multiplexing/demultiplexing device
15
-
12
in each of the ADSL packages
15
-
1
. The multiplexed data are then sent to the asymmetrical digital subscriber lines.
In the control package
15
-
2
, the cell multiplexing/demultiplexing device
15
-
21
further multiplexes the cell-multiplexed data output from the ADSL packages
15
-
1
, and send the resultant cell-multiplexed data to the ATM switch chip
15
-
22
. Further, the cell multiplexing/demultiplexing device
15
-
21
demultiplexes cell-multiplexed data output from the ATM switch chip
15
-
22
, and send demultiplexed cell data to the ADSL packages
15
-
1
.
Further, the cell multiplexing/demultiplexing device
15
-
25
multiplexes cell-multiplexed data output from the 155 Mbps interface package
15
-
3
, and send the resultant cell-multiplexed data to the ATM switch chip
15
-
22
. Further, the cell multiplexing/demultiplexing device
15
-
25
demultiplexes cell-multiplexed data output from the ATM switch chip
15
-
22
, and send demultiplexed cell data to the 155 Mbps interface package
15
-
3
.
The ATM Forum proposes an interface between the ATM layer device and the PHY layer device as a standardized interface in the ATM apparatuses that perform cell multiplexing and demultiplexing. Such a standardized interface is called UTOPIA.
The ATM Forum proposes some levels of UTOPIA. The Level 2 UTOPIA interface defines the interface of the single-stage structure in which a plurality of PHY layer devices are connected to a single ATM layer device (The ATM Forum Technical Committee “Utopia Level 2, v1.0”, af-phy-0039.000, June 1995, the disclosure of which is hereby incorporated by reference).
The Level 2 UTOPIA interface describes the following three definitions regarding the number of PHY layer devices, the cell format and the signal transmit and receive operation.
According to the first definition, the number of PHY layer devices that is allowed to be connected to one ATM layer device is limited up to eight when the transmission rate of the ATM layer is equal to 155 Mbps, and is limited up to four for 622 Mbps. 16 address spaces are allowed, and the upper limit on the number of address spaces is equal to 16 in practice.
The second definition prescribes two types of cell formats, one of which is a cell format in 8-bit mode and the other is a cell format in 16-bit mode. A user defined field (UDF) in the cell formats can be open to the user.
FIGS. 4A and 4B
respectively 8-bit mode and 16-bit mode cell formats in the Level 2 UTOPIA interface. As shown in
FIG. 4A
, the 8-bit mode cell format is made up of four headers #
1
-#
4
, the user defined area UDF and 48 payload fields #
1
-#
48
. As shown in
FIG. 4B
, the 16-bit mode cell format is made up of four headers #
1
-#
4
, two user defined fields #
1
and #
2
, and 48 payload fields #
1
-#
48
. As described above, the user is free to define the user defined field UDF of the 8-bit and the user defined fields UDF#
1
and UDF#
2
of the 16-bit mode.
The third definition prescribes the signal transmit and receive operation between one ATM layer device and a plurality of PHY layer devices (Multi-PHY). The signal transmit and receive operation uses one transmit-cell available signal
1
TxClav and one receive-cell available signal
1
RxClav. The third definition allows a direct status indication and a multiplexed status polling to be arbitrarily chosen.
A description will now be given, with reference to
FIGS. 5 through 8
, of the transmit and receive operation with the signals
1
TxClav and
1
RxClav.
FIG. 5
shows connections of signal lines between one ATM layer device
17
-
2
and a plurality of PHY layer devices
17
-
1
(#
1
-#N).
F
Chin Wellington
Katten Muchin Zavis & Rosenman
Schultz William
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