Multiplex communications – Data flow congestion prevention or control – Control of data admission to the network
Reexamination Certificate
1998-02-04
2001-11-27
Hsu, Alpus H. (Department: 2662)
Multiplex communications
Data flow congestion prevention or control
Control of data admission to the network
C370S235000, C370S392000, C370S395430, C370S399000, C370S429000, C370S465000, C370S474000
Reexamination Certificate
active
06324164
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The invention relates to telecommunication and more particularly to an ATM Protocol Adapter designed to be operated in high speed cell switch.
BACKGROUND ART
The need for higher speeding system is increasing, particularly with the development of more sophisticated networks, multimedia applications and high speed communications.
The requirements are such that today 100 Gigabits switches will be more and more needed. Therefore, there is a need for particular protocol adapters that are well suited for operating in combination with high speed switches, even in wide multicasting mode; that is to say, when the cell is duplicated towards different output ports.
Asynchronous Transfer Mode (A.T.M.) Is an important state in the evolution of the digital telecommunications.
Prior art document “A Highly Modular Packet Switch for Gb/s Rates” by W. E. Denzel, A. P. J. Engbersen, I. Illiadis, G. Karlsson in XIV International Switching Symposium, October 1992, Vol. 2, page A8.3 ff. relates to a high-speed switching system.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide an ATM Protocol Adapter that is particularly designed to operate with high speed switches, even when providing multicast capabilities.
This problem is solved by the Protocol Adapter, also called Protocol Engine, that has both a receive and transmit part based on a pipeline circuit, as defined herein.
An ATM Protocol Adapter for a high speed switching system comprising both a receive and transmit part based on pipeline structure ensuring that each operation is performed in a limited period. A particular arrangement of different tables provides the possibilities of performing the requirements technical operations on the cell in a limited period, thus permitting the use of the Protocol Adapter with high speed switching systems. More particularly, the receive part includes means (
920
) receiving the cell comprising a LI/VP/VC field, with LI defining from which line the cell entered into the Protocol Adapter, and VP/VC defining the ATM Virtual Path and Virtual Circuit assigned to the connection which the cell belongs. A first table (
920
) is accessed for providing an INPUT Index that is used for addressing a second table (
922
returning the following parameters assigned to the considered LI/VP/VC; a CONNECTION Index; a REASSEMBLY Index; an OPERATION AND MAINTENANCE (OAM) Index; a CELL EXTRACT Index; a SWITCH ROUTING HEADER (S.R.H.) Index used for controlling both the routing process and multicast operations that will be executed into the switching system; and an OUTPUT Index characterizing a specific operation which is to be performed in the destination Protocol Adapter that will receive the cell after it is routed throughout the switching system.
Each element of the receive pipeline structure used part of its corresponding index to perform the appropriate processing task before the cell is forwarded and processed by the next element of the pipeline structure.
A POLICING BLOCK (
925
) uses the CONNECTION Index for addressing a third table (POLICY AND PARAMETERS COUNTERS table
936
), that permits to check the conformance of the incoming cell to the Generic Cell Rate Algorithm (GCRA). Additionally, a AAL5 Block (
930
) uses the REASSEMBLY Index for determining whether the current cell should be reassembled in accordance with the AAL5 format or conversely forwarded to the next pipeline element without any reassembly. An OAM Block (
935
) uses the OAM Index for determining whether the received cell belongs to a connection for which a decision of OAM performance monitoring as specified in the 1.610 ITU Recommendation was made. A SWITCH HEADER INSERT Block (
940
) appends the SRH Index to the cell being processed by said receive pipeline circuit, which SRH Index will be used by the switching system for both controlling the routing and multicast operations therein performed. At last, the receive part comprises a VP/VO swap block (
945
) for inserting the OUTPUT Index within the cell in lieu of bits of said VP, and for further inserting a Header Correction Code (H.E.C.)
The invention also provides with a transmit part defined herein.
The arrangement of the receiver circuit in limited processing elements guarantees that the pipeline structure will be able to process the cells in a limited time, thus rending the Protocol Adapter well suited for high speed switching system.
REFERENCES:
patent: 5941952 (1999-08-01), Thomas et al.
patent: 5953538 (1999-09-01), Duncan et al.
patent: 6072798 (2000-06-01), Beasley
Luijten Ronald
Nicolas Laurent
Poret Michel
August Casey
Beck Thomas A.
Hsu Alpus H.
International Business Machines - Corporation
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