Asynchronous to synchronous particularly CMOS synchronizers

Details Asynchronous to synchronous particularly CMOS synchronizers Asynchronous to synchronous particularly CMOS synchronizers

1994-07-01

1995-05-23

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327141, 327185, 327333, H03L 700, A03K 3284

Patent

active

054184070

ABSTRACT:
The disclosure concerns asynchronous to synchronous synchronizers and particularly a technique which involves level shifting of a metastable voltage either within a synchronizer stage or between synchronizer stages. In a particular implementation of the invention, this level shifting is achieved by altering the relative proportions of at least one complementary pair of devices in a synchronizer or inserting diodes in order to shift the level of a metastable voltage outside the range of a fatal voltage window possessed or exhibited by an adjacent or following part or stage of the synchronizer. By this means, although the occurrence of a metastable condition cannot be avoided, the likelihood of propagation of the metastable condition throughout the synchronizer may be very significantly reduced.

REFERENCES:
patent: 4103188 (1978-07-01), Morton
patent: 4544851 (1985-10-01), Conrad et al.
patent: 4745302 (1988-05-01), Hanawa et al.
patent: 4796004 (1989-01-01), Rich et al.
patent: 4851710 (1989-07-01), Griona
patent: 5122694 (1992-06-01), Bradford et al.
Lindsay Kleeman & Antonio Cantoni, "Metastable Behavior in Digital Systems," IEEE Design & Test of Computers, Top-Down Layout for Custom Design Applications of Inverter-Free PLAs, 1987 Annual Index, Dec. 1987, pp. 4-19.
Stoll, How to Avoid Synchronization Problems VLSI Design, Nov./Dec. '82, pp. 56-57 and 59.
Kleeman, et al. Metastable Behavior in Digital Systems IEEE Design and Test of Computers, Dec. '87, pp. 4-19.
Flannagan, Synchronization Reliability in CMOS Technology IEEE Journal of Solid State Circuits, vol. SC-20, No. 4 Aug. 1985; pp. 880-882.
Horstmann, et al. Metastability Behavior of CMOS ASIC Flip-Flops in Theory and Test IEEE Journal of Solid State Circuits, vol. 24, No. 1; Feb. 1989; pp. 146-157.
Kim, et al. Metastability of CMOS Latch/Flip-Flop IEEE Journal of Solid State Circuits, vol. 25, No. 4; Aug. 1990; pp. 942-951.
Nootbar et al., Minimizing the Effect of Metastability in BiCMOS Circuit Design EDN Sep. 8, 1990; pp. 141-146.
Gabara, et al., Metastability of CMOS Master/Slave Flip-Flops IEEE 1991 Custon Integrated Circuits Conference pp. 29.4.1-29.4.6.
Masteller, Design a Digital Synchronizaer with a Low Metastable-Failure Rate EDN Apr. 25, 1991, pp. 169-174.
Rosenberger, et al., Comments on "Metastability of CMOS Latch/Flip-Flop" IEEE Journal of Solid State Circuits, vol. 27, No. 1, Jan. '92.

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