Asynchronous timing circuit for a 2-coordinate memory

Details Asynchronous timing circuit for a 2-coordinate memory Asynchronous timing circuit for a 2-coordinate memory

1990-08-13

1992-12-08

Popek, Joseph A.

Static information storage and retrieval

Addressing

Sync/clocking

365203, G11C 700

Patent

active

051703769

DESCRIPTION:

BRIEF SUMMARY
BACKGROUND OF THE INVENTION

1. Field of the Invention
The present invention relates to a control circuit for a 2-coordinate memory wherein an input signal is propagated through a memory row in order to derive a control signal for read or write operations.
2. Description of the Prior Art
Such a control circuit is already known in the art, e.g. from the article entitled "An 11-ns 8K.times.18 CMOS Static RAM with 0.5-um Devices" by D. T. WONG et al, published in the IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 23, NO. 5, October 1988 pages 1095 to 1103. Therein, the input signal is applied to one end of a reference row or word-line of the memory and the control signal is collected at the other end of this reference word-line. Since the reference word-line closely tracks the propagation time of a signal through an actual row or word-line of the memory, the control signal is used to restore a word-line selection signal within the active part of a read or write operation. This system has the advantage of automatically adapting the duration of a read or write operation to the length of the rows of the memory. However, to this end, the memory must be provided with a reference word-line whereby the propagation time of a signal through an actual word-line is simulated and the input signal must be applied to this reference word-line simultaneously with the application of a word-line selection signal to any word-line of the memory.


SUMMARY OF THE INVENTION

An object of the present invention is to provide a control circuit of the above known type but which does not require any reference word-line in the memory while keeping the above mentioned advantage.
According to the invention, this object is achieved due to the fact that said control circuit includes row selection means to apply said input signal to a desired row and coupling means to provide said control signal from any of said rows.
By applying the input signal to one end of the desired row or word-line of the memory, by collecting the signals at the other ends of all the word-lines and by coupling them with the coupling means one obtains the above control signal without using any reference word-line. In this way, apart from no reference word-line being required, the control signal reflects the actual propagation time of a signal through the desired row or word-line and is thus no longer a mere simulation thereof.
Another characteristic feature of the present invention is that said row selection means are used for selecting a row of said memory and in that said input signal is a row selection signal.
Since the above input signal is also the row or word-line selection signal, i.e. the desired row is also the selected row, there is no need to provide means for applying simultaneously the input signal on the reference word-line and the word-line selection signal to another word-line of the memory. The control circuit is thereby simplified.
The data busses or columns of the memory associated to the above control circuit need to be precharged at a predetermined voltage prior to each read or write operation. In the known control circuit, at least two control signals, one for controlling the precharging of the columns and another for controlling the read or write operation itself, are required. Moreover, to avoid signal collisions, the delay between, e.g., the end of a read (or write) operation and the beginning of the precharging of the columns may for instance be given by a timer controlled by a clock signal. This delay is then generally chosen too long for security reasons.
Another object of the present invention is to provide a control circuit of the above known type but wherein the delay between the end of a read or write operation and the beginning of the precharging of the columns is optimized.
According to the invention, this other object is achieved due to the fact that said control signal is used for activating a precharge signal which controls the precharging of the columns of said memory to a predetermined voltage level prior to a subsequent read or write

REFERENCES:
patent: 4712197 (1987-12-01), Sood
patent: 4918657 (1990-04-01), Takahashi
Patent Abstracts of Japan, vol. 11, No. 203 (P-591) (2650), 2 Jul. 1987.
IEEE Journal of Solid-State Circuits, vol. 23, No. 5, Oct. 1988, D. T. Wong et al.: "An 11-NS 8K.times.18 CMOS Static RAM with 0.5-Mum Devices".

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