Asynchronous time division switching arrangement and a method of

Details Asynchronous time division switching arrangement and a method of Asynchronous time division switching arrangement and a method of

1989-09-29

1993-05-18

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

370 941, H04Q 1104

Patent

active

052126862

ABSTRACT:
An asynchronous time division multiplex switching arrangement comprises a serial to parallel converter arranged to receive input packets of data which include routing information, in serial form and convert the packets of data to parallel form. A random access memory is provided in which each packet of data is entered at an addressed location into the memory, and the address is entered in a respective first-in first-out output queue at the tail. The address at the head of the queue is accessed and the packet of data is read from the random access memory into a parallel to serial converter and the packet of data is serially delivered to the associated output.

REFERENCES:
patent: 3914553 (1975-10-01), Melindo et al.
patent: 3979733 (1976-09-01), Fraser
patent: 4816823 (1989-03-01), Polkinghorne et al.
patent: 4910731 (1990-03-01), Sakurai et al.
Andrew K. Joy, et al Asynchronous Time Division Switching Arrangement and a Method of Operating Same.
#8823493.5, Oct. 6, 1988 and #8917530.1, Aug.1, 1989.

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