Asynchronous/synchronous pipeline dual mode memory access circui

Details Asynchronous/synchronous pipeline dual mode memory access circui Asynchronous/synchronous pipeline dual mode memory access circui

1989-09-13

1992-04-21

Gossage, Glenn

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

36523006, 365233, G11C 800, G11C 11418

Patent

active

051074656

ABSTRACT:
A pipeline memory access circuit has a memory address buffer for buffering memory addresses. The buffer has a first and a second pass gate, and each of the pass gates has a pair of complementary metal-oxide-semiconductor (CMOS) transistors. An apparatus is provided for selectively switching the buffer between an asynchronous and a synchronous mode of operation. The switching apparatus includes circuits for alternately opening and closing the first and second pass gates when the buffer is in its synchronous mode of operation and for simultaneously opening both of the pass gates when the buffer is in its asynchronous mode of operation.

REFERENCES:
patent: 4415994 (1983-11-01), Ive et al.
patent: 4750839 (1988-07-01), Wang et al.
patent: 4849935 (1989-07-01), Miyazawa
patent: 4912679 (1990-03-01), Shinoda et al.

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