Asynchronous superconductor serial multiply-accumulator

Details Asynchronous superconductor serial multiply-accumulator Asynchronous superconductor serial multiply-accumulator

2000-11-13

2002-05-14

Jeanpierre, Peguy (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S133000

Reexamination Certificate

active

06388600

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to a system that converts an analog signal to a digital signal having a lower frequency representation and, more particularly, to an oscillator/multiply-accumulator analog-to-digital converter that simultaneously performs frequency downconversion, band pass filtering and analog-to-digital conversion of an analog signal using a superconducting, Josephson single flux quantum circuit to extract information from a modulated carrier wave in a communications system.
2. Discussion of the Related Art
Various communication systems, such as cellular telephone systems, radar systems, etc., transmit information by modulating the information to be transmitted onto a high frequency carrier signal. Different modulation techniques are known in the art, such as amplitude modulation, frequency modulation, phase modulation, etc., that impress information onto a carrier signal to be transmitted. The carrier signal is received by a receiver that removes the carrier signal to separate and decipher the transmitted information. To remove the carrier signal, state of the art receivers typically include an analog mixer or a frequency downconverter that multiplies the received carrier signal with a local oscillator signal to remove the carrier signal and convert the signal to a lower intermediate or baseband frequency. The downconverted frequency signal is then filtered by a pass band filter that passes the frequencies of interest including the extracted information. The filtered signal is then converted to a digital signal by an analog-to-digital (A/D) converter to provide a digital representation of the information that is subsequently processed by a digital microprocessor. This process for extracting information from a carrier signal is well known to those skilled in the art.
Although this type of circuit is successful for extracting transmitted information from a carrier signal, improvements can be made. For example, because these types of communication systems first mix the analog carrier signal to provide the downconversion and then filter the downconverted analog signal before the signal is converted to a digital representation, noise from the various amplifiers and other electrical components in the downconverter and filter decreases the signal-to-noise ratio of the signal and thus degrades the receiver performance. Additionally, it takes several discrete electrical circuits to perform the mixing, filtering and analog-to-digital conversion. Therefore, the communication electronics could benefit from decreased complexity, part count, and power consumption of these circuits.
Alternately, frequency downconversion can be performed digitally. A straight-forward method of digitally performing frequency downconversion is to digitize the carrier signal fast enough to record the carrier directly. In principle, the information on the carrier signal can be extracted from the digital data stream using fast Fourier transform (FFT) routines and other digital signal processing techniques. This type of method stresses the performance of the A/D converter, because it needs to sample the signal fast enough to record the carrier while maintaining a very high dynamic range to avoid degrading the signal and the information bandwidth. Because of this requirement, these systems would require an A/D converter performance which cannot yet be realized in the state of the art.
A second digital frequency downconversion technique, presently used to effectively produce frequency downconversion, is known as intermediate frequency (IF) sampling. In IF sampling, a narrow band pass analog filter centered at the carrier frequency, precedes a standard non-integrating A/D converter. The A/D converter is intentionally operated well below the Nyquist condition for the input signal, generating an alias of the signal which effectively converts the frequency of the information. The presence of the narrow band pass filter removes the ambiguity in the original signal frequency usually introduced by aliasing in A/D conversion. This technique is fundamentally different from the present invention. IF sampling is based on instantaneous samples of the signal where the sampling is done on a time scale very short compared to one period of the carrier signal. The present invention is based on an integration of the signal over a time longer than a few periods of the carrier signal. This difference leads to significantly different requirements for the analog signal filter and much greater flexibility of the present invention.
Oscillator/counter A/D converters that use superconducting, Josephson single flux quantum (SFQ) circuits for converting an analog signal to a digital signal are disclosed in U.S. Pat. No. 5,942,997. A general depiction of an oscillator/counter A/D converter
10
of the type disclosed in Pat. No. 5,942,997 is shown in FIG.
1
. The converter
10
includes a voltage controlled oscillator (VCO)
12
, a digital gate circuit
14
and a digital pulse counter circuit
16
. Each of the VCO
12
, the gate circuit
14
and the counter circuit
16
are general representations of known electrical circuits that perform the functions described herein. The analog carrier signal is received by an antenna (not shown) and is applied to the VCO
12
. The VCO
12
converts the analog signal to a series of high frequency SFQ pulses having a pulse frequency proportional to the voltage potential of the analog signal applied to the VCO
12
. The VCO
12
uses multiple Josephson Junctions within a direct current superconducting quantum interface device (SQUID) to convert the analog signal to the series of SFQ pulses. The repetition rate of the pulses from the VCO
12
is dependent on the frequency and amplitude of the carrier signal and the information modulated thereon. In other words, the VCO
12
will output the pulses at a certain pulse rate depending on the characteristics of the modulated carrier signal. Typically, the pulse rate of the output of the VCO
12
will be greater than the frequency of the carrier signal.
A control signal is applied to the gate circuit
14
such that when the control signal is high, the gate circuit
14
will pass the pulses from the VCO
12
. When the gate circuit
14
passes the pulses from the VCO
12
, the counter circuit
16
accumulates and counts the pulses to give a digital representation of the analog input signal to the VCO
12
. In one embodiment, the counter circuit
16
is a single flux quantum counter comprising a chain of flip-flops which operate asynchronously to accumulate the total number of pulses from the VCO
12
. The total count of the pulses from the VCO
12
during the time that the control signal to the gate circuit
14
is high is the digital representation of the analog signal integrated over the sample time. The oscillator/counter A/D converter disclosed in U.S. Pat. No. 5,942,997 resets the counter circuit
16
to zero before each sample time. In other words, each time the control signal applied to the gate circuit
14
goes low, the counter circuit
16
is reset so that the sample period is equal to the period of the gate control pulses.
Attempts have been made to improve the control of the oscillator/counter A/D converter of the '997 patent. These attempts are discussed in U.S. Pat. No. 6,127,960, U.S. patent application Ser. No. 09/326,073, filed Jun. 4, 1999, referenced above.
As is best illustrated in
FIGS. 1 and 2
, the '960 patent discloses the analog input signal
20
being input into the VCO
12
, where it is converted into a series of sharp, high frequency pulses based on the characteristics of the carrier signal. The series of pulses are applied to a gate circuit
14
that either passes or blocks the pulses depending on whether the gate control signal is high
22
or low
24
. When the pulses are passed by the gate circuit
14
, the counter circuit
16
accumulates the pulses during a sampling period T. The sampling period T covers a range of gate control pulses
22
and
24
so th

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