Pulse or digital communications – Spread spectrum – Direct sequence
Patent
1992-03-04
1994-11-22
Bocure, Tesfaldet
Pulse or digital communications
Spread spectrum
Direct sequence
375120, H04L 7027
Patent
active
053675452
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention provides an asynchronous signal extracting circuit for extracting asynchronous signals that are multiplexed in a synchronization frame.
BACKGROUND ART
A synchronous digital hierarchy (SDH) for transmitting asynchronous signals in a multiplexed form in a synchronization frame has been standardized as recommended by CCITT (International Telegraph and Telephone Consultative Committee) and T1 Committee of U.S.A. In the synchronous digital hierarchy, it is necessary to extract asynchronous signals from the received signals in order to obtain valid data accompanying almost no jitter.
In the synchronous digital hierarchy (SDH) recommended by CCITT, a difference in speed between the synchronous system and the asynchronous system is corrected by a pointer adjustment function; i.e., invalid data consisting of eight bits is inserted or deleted by the pointer adjustment, and a phase jump of eight bits takes place in the formation payload. The phase jump causes jitter that is given to asynchronous signals extracted from the synchronous multiplexed signals that are received. On the receiving side, therefore, the jitter must be suppressed by using phase-locked loop circuit or a like circuit.
On the receiving side in the conventional synchronous digital hierarchy as will be described later in detail, valid data only are written using a buffer memory when the asynchronous signals are to be extracted by receiving synchronous multiplex signals, and the valid data are read out according to read clock signals. Here, the write clock signals of a buffer memory have an untoothed period that varies depending upon the presence or absence of pointer adjustment, and the moment at which the pointer adjustment takes place is not definite, resulting in the occurrence of low-frequency jitter as described above.
As a means for reducing the low-frequency jitter, for example, the Contribution (T1X1.6/89-020R2) of T1X1.6 of U.S.A. discloses circuits and problems. The circuits are:
(1) A desynchronizer (asynchronous signal extracting circuit) equipped with a PLL of a very low frequency band;
(2) A synchronous desynchronizer;
(3) A fixed bit leak circuit (using PLLs in two stages); and
(4) A two-stage PLL of the linear digital control type.
The circuit (1) requires a PLL of a frequency band as narrow as about 3 Hz with which it is difficult to realize a practical circuit.
The circuit (2) requires digital control that adapts to the monitoring of a buffer memory, which results in a complex circuit apparatus and control operation.
In the circuit (3), the bits slowly leak over a given period of time as the pointer adjustment takes place, and the jitter component decreases. Here, however, the buffer memory must have an extra capacity to cope with the pointer adjustment that takes place continuously.
The circuit (4) requires a digital filter or a dither, causing the circuit apparatus to become complex.
SUMMARY OF THE INVENTION
In view of the above-mentioned defects, the object of the present invention is to suppress the low-frequency jitter relying upon a simple apparatus.
In order to achieve the above object according to the present invention, a control is applied to the frequency band of a low-pass filter mounted in a phase-locked loop circuit that forms the read clock signals that will be applied to the buffer memory. The low-frequency jitter is suppressed by controlling the frequency band.
BRIEF DESCRIPTION OF DRAWINGS
The invention will now be described with reference to the accompanying drawings wherein:
FIG. 1 is a block diagram showing major portions of the receiving side in a conventional synchronous digital hierarchy;
FIGS. 2A to 2H are diagrams of signals for explaining the operation of the conventional example of FIG. 1;
FIG. 3 is a block diagram showing the principle and apparatus of an asynchronous signal extracting circuit according to the present invention;
FIG. 4 is a block diagram showing the asynchronous signal extracting circuit according to an embodiment of the present invention;
F
REFERENCES:
patent: 4095053 (1978-06-01), Duttweiler et al.
patent: 4667324 (1987-05-01), Graves
patent: 5245636 (1993-09-01), Sari et al.
Holborow et al., "Synchronization of Transmission Systems," IEEE International Conference on Communications '88, vol. 2, Jun. 12, 1988, pp. 895-898.
Sabit Say, "Bellcore: Contribution To T1 Standards Project," A Synchronous Desynchronizer, Jul. 25, 1988, pp. 1-7.
Takizawa Yuji
Yamashita Haruo
Bocure Tesfaldet
Fujitsu Limited
LandOfFree
Asynchronous signal extracting circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Asynchronous signal extracting circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Asynchronous signal extracting circuit will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1996121