Coded data generation or conversion – Digital code to digital code converters – Serial to parallel
Reexamination Certificate
1999-10-19
2003-04-08
Young, Brian (Department: 2819)
Coded data generation or conversion
Digital code to digital code converters
Serial to parallel
Reexamination Certificate
active
06545617
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an asynchronous serial data receiving device and an asynchronous serial data transmitting device, which are connected to or installed in a data processing device such as a microcomputer or the like, and more particularly relates to an asynchronous serial data receiving device and an asynchronous serial data transmitting device, which operate data communication based on the asynchronous data receiving and transmitting method capable of controlling the data reception conducted at the receiving device in the case where sampling interval between each of the bits forming a communication data is not constant, and also controlling the data transmission conducted at the transmitting device in the case where transmission interval between each of the data forming bits is not constant.
2. Description of the Related Art
Methods of communication between different microcomputers or between a microcomputer and a peripheral device are classified into two methods; namely a method in which data are received and/or transmitted in parallel per each data unit formed by a plurality of bits, and a method in which data are received and/or transmitted in serial per each data bit. The method in which data are received and/or transmitted in parallel can communicate more data per unit time than the case in which data are received and/or transmitted in serial. However, the former method requires many more cable distributions, which thereby increases the total cost for communications overall.
On the other hand, the methods in which data are received and/or transmitted in serial can be further classified into two communication methods; namely the synchronous serial data transmission and/or reception method in which the timing for synchronization between the transmission side and the reception side is adjusted by use of a clock signal, and the asynchronous serial data transmission and/or reception method in which no clock signal is used for adjusting the timing for synchronization. Since the asynchronous serial data transmission and/or reception method requires no clock signal, although it requires less cable distributions than those of the synchronous serial data transmission and/or reception method, its operation speed tends to be slow.
FIG. 23
is an exemplary view showing the general idea of a receiver section and a transmitter section in the asynchronous serial data communication system. In the figure, reference numeral
220
denotes an asynchronous serial data transmitting device as the transmitter section in the asynchronous serial data communications, numeral
221
denotes an asynchronous serial data receiving device as the receiver section in the asynchronous serial data communications, numeral
223
denotes a communication enable signal which is output from the receiver section
221
, and input to the transmitter section
220
, and reference numeral
224
denotes a communication data which is output from the transmitter section
220
, and input to the receiver section
221
.
The operation in the conventional asynchronous serial data communication system is now explained below.
FIG. 24
is an exemplary view showing an example of the communication data format used in the asynchronous serial data communications. In the figure, reference numeral
5
denotes a start bit which is a one-bit signal of the logic low level,
6
denotes a data bit,
7
denotes a parity bit which is added to the communication data in order to improve reliability of the data, and reference numeral
8
denotes a stop bit for indicating the end of the data transmission, which is formed by either one-bit signal or two-bit signal of the logic high level.
“Parity” includes an even parity which sets the parity bit in such a manner that the number of bits of the logic “1” (hereinafter may be referred to as “logic high level” or just as “high”) in the communication data formed by the total number of data bits
6
and parity bit
7
becomes a certain even number, and also includes an odd parity which sets the parity bit in such a manner that the number of bits of the logic “1” in the communication data formed by the total number of data bits
6
and parity bit
7
becomes a certain odd number. There is also communication data which requires no parity bit.
FIG. 25
is a block diagram of the conventional asynchronous serial data receiving device as the receiver section
221
. In the figure, reference numeral
252
denotes a serial-to-parallel conversion circuit which inputs a communication data
224
on the basis of a data shift signal
254
, and converts it from the serial data to the parallel data
253
.
FIG. 26
is a timing chart indicating the operation of the serial-to-parallel circuit
252
shown in FIG.
25
. When the receiver section
221
is in the state in which it can receive the data signal, it sends a communication enable signal
223
by setting it to the logic low level to the transmitter section
220
. The transmitter section
220
recognizes that the communication enable signal is in the low level, and sends a binary data signal “0101001001”.
On this occasion, the start bit
5
has been added to the head portion of the binary data signal to be transmitted, and also the stop bit
8
has been added to the last portion of the data. The receiver section
221
receives the communication data
224
, detects the start bit
5
and starts receiving the entire communication data
224
.
The same baud rate is set to both the transmitter section
220
and the receiver section
221
, wherein the reception and transmission of the communication data are executed in accordance with the thus set baud rate.
Under the ideal condition, the value of the communication data
224
is taken into the serial-to-parallel conversion circuit
252
at the center of each bit. In
FIG. 26
, the communication data
224
is taken into the serial-to-parallel conversion circuit
252
, when the data shift signal
254
is changed from high to low.
Since the conventional asynchronous serial data transmitting and receiving devices are configured as such, the transmitter section
220
and the receiver section
221
generally operate at different operation clocks from each other. For this reason, since the time required for communicating a data of one bit can be set only to a time period whose length is a multiple of integer of an operation clock cycle, even in a case where the same baud rate is set to both the transmitter section
220
and the receiver section
221
, there has been caused a setting error of the baud rate.
FIG. 26
shows an example of the operation in the case where the receiver section
221
receives a communication data formed by eight data bits
6
and one data bit
8
, when the communication time for one-bit data is set to the time period corresponding to four cycles of the clock signal
11
used therein.
In the figure, it is arranged in such a manner that when the data shift signal
254
is changed from the high level to the low level, the communication data
224
is taken into the serial-to-parallel conversion circuit
252
, and the data taken into the serial-to-parallel conversion circuit
252
is formed as “101000100” excluding the start bit
5
.
In the example shown in
FIG. 26
, a communication data receiving error can be observed at the sixth, seventh and ninth bits of the communication data
224
. If the baud rate set in the case of
FIG. 26
is made smaller, the communication time for one-bit data is made longer, so that occurrence of the baud rate setting error with respect to the communication time for one-bit data can be efficiently suppressed.
For this reason above, in the actual case of the asynchronous serial data transmitting and receiving devices, there has been such a problem that the largest baud rate has to be suppressed down to the level in which no data receiving error occurs.
SUMMARY OF THE INVENTION
The present invention has bee n proposed to solve the problems aforementioned, and it is an object of the present invention to provide an
Burns Doane , Swecker, Mathis LLP
Mitsubishi Denki & Kabushiki Kaisha
Young Brian
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