Asynchronous semiconductor memory device with a control...

Details Asynchronous semiconductor memory device with a control... Asynchronous semiconductor memory device with a control...

1999-05-18

2001-04-03

Nelms, David (Department: 2818)

Static information storage and retrieval

Addressing

Sync/clocking

C365S195000, C365S189050

Reexamination Certificate

active

06212125

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a semiconductor memory device, in particular, it relates to a semiconductor memory device provided with a control circuit which enables to increase timing margins of input setup time (hereinafter referred to as “TSI”) and input hold time (hereinafter referred to as “THI”) of a high speed dynamic random access memory (hereinafter referred to as “DRAM”).
BACKGROUND OF THE INVENTION
A synchronous dynamic random access memory (hereinafter referred to as “SDRAM”) is known as a storage medium which can be operated at high speed synchronizing with a clock signal input from an external terminal. As a SDRAM is designed to acquire all inputs at the rising edge from low state to high state of a system clock of an external input signal, a D-type flip-flop control circuit (hereinafter referred to as “control circuit”) is usually used for acquiring input signals.
Constitution and operation of a prior control circuit
80
will be explained with reference to of FIG.
12
and the timing chart shown in FIG.
13
. The control circuit
80
includes a first input part
81
, a second input part
82
, a latch signal generating part
84
and an output part
85
as its main components.
When an external input signal CLK generated from an external device such as CPU, is input to the first input part
81
, a row address intake signal IN
1
generated synchronizing with the external input signal CLK is transmitted through serially connected inverters
100
,
102
,
104
,
106
sequentially, and a signal
107
output from the last inverter
106
is input to the latch signal generating part
84
.
At this stage, the signal
107
is branched into two, one of which is input to one input of a NAND gate
114
through multiple and odd numbers of inverters
108
,
110
and
112
. The other signal is input directly to another input of the NAND gate
114
. Responding to the time difference of two input signals input to the NAND gate
114
, a row address latch signal LAT is output from the NAND gate
114
to the one-shot output part
85
. In other words, when the row address intake signal IN
1
rises from low to high state, the row address latch signal LAT as a one-shot signal generated in response to the rising edge of the signal IN
1
, is output to the output part
85
.
On the other hand, when an external input signal A
0
generated from an external device such as CPU, is input to the second input part
82
, a row address intake signal IN
2
generated synchronizing with the external input signal A
0
is transmitted through serially connected inverters
120
,
122
,
124
,
126
sequentially, and a signal A
0
D output from the last inverter
126
is input to the output part
85
.
At the output part
85
, the row address latch signal LAT output from the latch signal generating part
84
is input to a gate of a PMOS
127
, a gate of a NMOS
128
through an inverter
134
, and a gate of a NMOS of a clocked inverter
132
, respectively. The signal A
0
D which is output from the second input part
82
through the inverters
120
,
122
,
124
and
126
sequentially is input to a source of the PMOS
127
and a drain of the NMOS
128
, respectively.
The PMOS
127
and the NMOS
128
is turned into on state, when the row address intake signal LAT is in low state, acquire the signal A
0
D and output a signal A
0
H. The signal A
0
H is transmitted through serially connected inverters
129
and
131
, and an inner row address signal A
0
X is output from the last inverter
131
. An output of the inverter
129
is input to the clocked inverter
132
as well as to the inverter
131
. The output of the clocked inverter
132
is again input to the inverter
129
. The clocked inverter
132
is inhibited to output a signal as long as the row address latch signal LAT remains in low state, thereby the signal A
0
H is unlatched. When the row address latch signal LAT rises from low state to high state, the clocked inverter
132
latches the signal A
0
H to inhibit the switching of the inner row address signal A
0
X.
Next, a TSI standard and a THI standard will be explained with reference to the timing chart shown in FIG.
13
. The TSI standard relates to a time interval between the falling edge of the external input signal A
0
from high state to low state at a time T
1
, and the rising edge of the external signal CLK from low state to high state at a time T
2
, (T
2
−T
1
). The TSI standard is set as the standard of a device. The THI standard relates to a time interval between the rising edge of the external signal CLK from low state to high state at the time T
2
, and the rising edge of the external input signal A
0
from low state to high state at a time T
3
(T
3
−T
2
). The THI standard is also set as a standard of the device.
As shown in
FIG. 13
, with the falling edge of the external input signal A
0
from high state to low state at the time T
1
the signal IN
2
and the signal A
0
D are switched from high state to low state sequentially. In response to the falling edge of the row address latch signal LAT from high state to low state, the PMOS
127
and the NMOS
128
output the state of the signal A
0
D to the signal A
0
H. The clocked inverter
132
inhibits the switching of the signal A
0
H in response to the rising edge of the row address latch signal LAT from low state to high state. That is, when the external input signal A
0
rises from low state to high state in accordance with the TSI standard, a float time TA, which is the time interval between the falling edge of the signal A
0
H from high state to low state and the rising edge of the row address latch signal LAT from low state to high state, is caused.
Consequently, as shown in the timing chart of
FIG. 14
, it is made possible to delay the falling edge of the external signal A
0
till a time T
1
at which the value of the float time TA becomes 0. As a result, the time interval between T
1
and T
1
′(T
1
′−T
1
) is obtained as a TSI margin.
As also shown in
FIG. 13
, when the external signal A
0
is turned from low to high state at the time T
3
, the signal IN
2
and the signal A
0
D are switched from low to high state sequentially. On the other hand, in response to the rising edge of the row address latch signal LAT from low to high state, the NMOS
127
and the PMOS
128
inhibit the state of the signal A
0
D from being output to A
0
H. Accordingly, when the external input signal rises from low to high state in accordance with the THI standard, a float time TB between the rising edge of the row address latch signal LAT and the rising edge of the signal A
0
D is obtained.
Consequently, as shown in the timing chart of
FIG. 15
, it is made possible to advance the rising edge of the external signal A
0
to a time T
3
′ at which the value of the float time TB becomes 0. As a result, the time interval between T
3
and T
3
′ (T
3
−T
3
′) is obtained as the THI margin.
In the control circuit
80
according to the prior art, the TSI margin can be increased by delaying the rising edge of the row address latch signal LAT from low to high state and thereby increasing the float time TA. However, the decrease of the float time TB resulted from delay of the rising edge of the row address latch signal LAT causes decrease of the THI margin.
On the other hand, the THI margin can be increased by advancing the rising edge of the row address latch signal LAT from low to high state and thereby increasing the float time TB. However, the decrease of the float time TA resulted from the advance of the rising edge of the row address latch signal LAT causes a decrease of the TSI margin.
SUMMARY OF THE INVENTION
The present invention has been made in view of the above-mentioned problem, in association with the prior art semiconductor memory device. Therefore an object of the invention is to provide a novel and improved semiconductor device wherein timing margins of both TSI and THI standards of SDRAM can be increased.
In order to solve the above-mentioned problem, according to the fir

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