Coded data generation or conversion – Digital code to digital code converters – Data rate conversion
Reexamination Certificate
2007-03-22
2008-08-05
Jeanglaude, Jean B (Department: 2819)
Coded data generation or conversion
Digital code to digital code converters
Data rate conversion
C708S313000, C708S300000
Reexamination Certificate
active
07408485
ABSTRACT:
A sample rate converter suitable for use in an audio DAC includes a first estimating circuit (32A) generating first (TR) and second (STAMPR) signals synchronized to an asynchronous clock (MCLK) and representing the period and edge arrival times, respectively, of a reference clock (REFCLK). A second estimating circuit (32B) operates on the first and second signals to generate third (T1) and fourth (STAMP1) signals representing an input sample rate (32fsin) and arrival times of input data samples, respectively, which are applied to a coefficient and address generator (76) to generate read addresses and coefficients input to a FIFO memory (42) receiving digital input data at the input sample rate and a multiplication/accumulation circuit (78) receiving data from the FIFO memory. The multiplication/accumulation circuit produces an output signal (SRC-out) synchronized to the asynchronous clock at an output sample rate (32fsout).
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Sculley Terry L.
Yu Shawn Xianggang
Brady III Wade J.
Jeanglaude Jean B
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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