Asynchronous queuing circuit for DRAM external RAS accesses

Details Asynchronous queuing circuit for DRAM external RAS accesses Asynchronous queuing circuit for DRAM external RAS accesses

2002-08-02

2003-11-04

Mai, Son (Department: 2818)

Static information storage and retrieval

Addressing

Sync/clocking

C365S233500, C711S167000

Reexamination Certificate

active

06643216

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to dynamic random access memories (DRAMs) with an SRAM-type interface and, more particularly, to a technique for queuing a new DRAM external access request to the DRAM while a current access cycle is still in progress.
2. Prior Art
Previously, external accesses to an ordinary DRAM have been constrained to follow a conventions that requires that a new external access cannot be initiated until a current external access cycle is completed. However, with the advent of DRAM devices with an SRAM-type interface, these DRAMS must be able to respond to any asynchronous access request inputs that may occur during an external access RAS cycle. To preserve the integrity of whatever data is being transferred during an external access cycle, a DRAM device with an SRAM-type interface must complete a current RAS cycle prior to beginning execution of a new external access cycle.
Consequently, a need exists for a DRAM device with an SRAM-type interface that allows external access operations to be initiated while a current external access cycle is still in progress.
SUMMARY OF THE INVENTION
The present invention provides a more general interface protocol for a DRAM device that has a SRAM-type interface. External row-access-select (RAS) requests to a DRAM device that has a SRAM-type interface are provided for initiating a RAS cycle in which external data is written into the DRAM or in which data in the DRAM is read out to an external location. The present invention provides queuing of external access requests and allows new external RAS access cycles to the DRAM to be initiated prior completion of a current external access cycles.
The present invention provides a queuing circuit that queues a request for a new external access and that subsequently executes a corresponding RAS cycle for that new request after completion of a current external access cycle.
An external access request precedes execution of a RAS cycle. The external access request initiates a RAS cycle. When no current external access RAS cycle is currently underway, that is, when no RAS request is currently being processed, the present invention provides that a first request latch or similar storage element is set in response to an initial access request. When access to the memory begins in a RAS cycle, this first request latch is reset.
In the case where a first RAS cycle is currently being processed, a second in-progress latch or similar storage element is set in response to a new, second access request that occurs. When the first RAS cycle is completed, if the second in-process latch is set, a new RAS cycle is initiated for the second access request and both the first and the second latches are reset. Any subsequent new external access requests are queued if the subsequent new access request arrives prior to completion of a current second access cycle.
The present invention provides for a more general asynchronous interface for a DRAM device. Without the invention, external accesses are constrained to follow the DRAM convention that requires that a new access cannot be started until the current access cycle is completed. With the invention, accesses can be initiated sooner and they are queued by the circuits of the present invention.
The present invention provides an method and a circuit for queuing asynchronous external memory requests that initiate external RAS cycles of a DRAM. The external-access request queuing circuit includes an address transition circuit that responds to changes in address input signals for the DRAM by providing an address change detection signal (det_a_buf) and, if an address input signal is stable, provides a stable address signal (addr_stable). A RAS timer circuit receives an input selection trigger signal (sel_xras) to provide a RAS output signal (xras_time
1
_b or xras
1
_b) that controls execution of external RAS cycles by the DRAM.
The invention provides a pair of latches. When there is no RAS cycle currently underway, a first latch is set in response to a stable address signal (addr_stable) to thereby provide an output signal (xr_rq) that initiates an input selection trigger signal (sel_xras)for the RAS timer circuit. The first latch is reset whenever execution of an external RAS cycle begins.
While a current RAS access cycle is underway, a second queuing latch is set in response to an address change detection signal (det_a_buf). The second latch provides a request-queue output signal (xque) that is used when the RAS output signal goes inactive to alternatively help initiation of the input selection trigger signal (sel_xras) for the RAS timer circuit.
If the second queuing latch is set and when any RAS access cycle is complete, a new RAS cycle is initiated and the second queuing latch is reset. The invention provides that any new access requests, as indicated by the address change detection signal (det_a_buf), that are received when a current RAS access cycle is underway are queued in the second queuing latch to await execution of a corresponding RAS cycle.
The second latch has associated with it a queuing logic gate that provides an active xque_start_b for initiating the input selection trigger signal (sel_xras) for the RAS timer circuit signal upon receipt of an active xque signal, an inactive addr_stable signal, and an inactive xras
1
_b signal. The active xque_start_b signal also resets the second queuing latch.
In one embodiment of the invention, the first latch is an RS flip-flop circuit having an active output signal xr_rq that is set by the addr_stable signal going inactive when the xras_time
1
_b signal is inactive and that is reset when the xras_time
1
_b begins to be active.
In this embodiment of the invention, the second queuing latch is a D flip-flop circuit with an output signal xque. The D flip-flop has a D input terminal for receiving the xras_l signal a clock terminal for receiving an output signal from a 2-input AND gate that receives a det_a_buf signal from the address transition detection circuit and that receives an inverted xque signal.
A queuing logic gate provides an active xque_start_b output signal upon receipt of an active xque signal, an inactive addr_stable signal, and an inactive xras
1
_b signal. The active xque_Start_b signal also resets the D flip-flop.
The RAS output signal from the RAS timer circuit has a predetermined active time for controlling execution of an external RAS cycle by the DRAM. A collection NAND gate receives the active xque start_b signal or the active output signal xr_rq to provide an active sel_xras signal from the RAS timer circuit.
A method is provided for queuing asynchronous external memory requests for external RAS cycles of a DRAM having an SRAM-type interface. In response to any changes in address signals for the DRAM, the methods provides for generating a det_a_buf signal and generating an address stable signal addr_stable if the new address is stable. If there is no RAS cycle currently underway, then the addr_stable signal is used to latch a first RAS request signal in a first latch. In response to the latched first RAS request signal, a first RAS cycle is initiated. The first latch is reset when the first RAS cycle begins. If the first RAS cycle is currently underway, a subsequent, second RAS cycle request signal is latched into a second latch using the det_a_buf signal.
When the first RAS cycle is complete and, if the second latch contains a second RAS cycle request signal, a second RAS cycle is initiated for the second RAS cycle request and the second latch is reset when the second RAS cycle begins and the addr_stable signal is used to latch the first RAS request signal in the first latch.


REFERENCES:
patent: 6134638 (2000-10-01), Olarig et al.
patent: 6209071 (2001-03-01), Barth et al.

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