Asynchronous pulse discriminating synchronizing clock pulse gene

Details Asynchronous pulse discriminating synchronizing clock pulse gene Asynchronous pulse discriminating synchronizing clock pulse gene

1997-03-28

1999-06-29

Tran, Toan

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327141, 327162, H03K 1722, H03L 700

Patent

active

059173505

ABSTRACT:
A programmable device includes circuitry for generating an asynchronous logic derived clock signal from one or more of a plurality of input signals. Further circuitry for synchronizing the asynchronous logic derived clock signal to a reference clock signal is coupled to the generating circuitry. The synchronizing circuit generates a synchronized logic derived clock signal from the asynchronous logic derived clock signal and the reference clock signal. The synchronized logic derived clock signal is produced only when the input signals from which the asynchronous logic derived clock signal is created are recognized as proper input signals and the synchronized logic derived clock signal has a fixed duration logic HIGH interval for variable duration logic HIGH intervals of the input signals. Spurious input signals or noise are rejected. Further, the programmable device includes circuitry for suspending a clock signal by logically combining the synchronized logic derived clock signal with the reference clock signal.

REFERENCES:
patent: 4973860 (1990-11-01), Ludwig
patent: 5001374 (1991-03-01), Chang
patent: 5418407 (1995-05-01), Frenkil
patent: 5522048 (1996-05-01), Offord

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