Asynchronous pseudo SRAM and access method therefor

Details Asynchronous pseudo SRAM and access method therefor Asynchronous pseudo SRAM and access method therefor

2006-02-21

2006-02-21

Nguyen, Tuan T. (Department: 2824)

Static information storage and retrieval

Addressing

C365S230060, C365S230080

Reexamination Certificate

active

07002871

ABSTRACT:
A semiconductor integrated circuit device includes an address buffer which receives an address signal that indicates an address of a memory cell array, a latch circuit which latches the data, and an address transition detection circuit which detects transition of the address. During the access operation of the memory cell array, an address at the operation start time is latched by the latch circuit. After the end of the operation of the memory cell array, an address that is currently input to the address buffer is latched by the latch circuit. If the received address signal is data different from the latch data, a control signal that controls the cycle operation of the memory cell array for a predetermined period is generated on the basis of the detection result from the address transition detection circuit.

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