Asynchronous pseudo SRAM

Details Asynchronous pseudo SRAM Asynchronous pseudo SRAM

2005-05-10

2005-05-10

Le, Thong Q. (Department: 2818)

Static information storage and retrieval

Addressing

Sync/clocking

C365S230080

Reexamination Certificate

active

06891775

ABSTRACT:
An ATD circuit for row access, an ATD circuit for column access, and a mode determination circuit which determines which of the row access mode and column access mode is being executed are arranged in a pseudo SRAM. A mode determination signal is automatically generated in the chip to control the internal circuits. Upon detecting column address transition after the start of the cycle and activation of the sense amplifier, the mode determination circuit determines that column access starts. Upon detecting transition of a row address or a predetermined mode address after consecutive transition of the column address, the mode determination circuit determines that the column access mode is ended.

REFERENCES:
patent: 5258952 (1993-11-01), Coker et al.
patent: 6-12617 (1994-02-01), None
patent: 7-70214 (1995-07-01), None
patent: 2002-269977 (2002-09-01), None

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