Asynchronous priority circuit for controlling access to a bus

Details Asynchronous priority circuit for controlling access to a bus Asynchronous priority circuit for controlling access to a bus

1977-06-06

1979-04-03

Yusko, Donald J.

Communications: electrical

Digital comparator systems

340147SY, 364900, G05B 2300, G06F 900, H04Q 300

Patent

active

041480112

ABSTRACT:
A priority arbitration circuit for resolving priority between a plurality of master devices which compete for access to one or more slave devices over a common bus. All master devices share a common Request line and a common Busy line. Priority is passed along serially from one device to another in sequence until all pending requests have been serviced, after which priority reverts to an initial device. The first device to issue a request gains priority. Simultaneous requests are resolved in the order in which the devices are connected in the priority chain. A device having a local request and receiving priority on the priority chain sets the Busy signal to lock out all other devices.

REFERENCES:
patent: 3699529 (1972-10-01), Beyers et al.
patent: 3796992 (1974-03-01), Nakamura et al.
patent: 3832689 (1974-08-01), Means et al.
patent: 4016539 (1977-04-01), Nanya

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