Electrical computers and digital processing systems: processing – Processing architecture – Data driven or demand driven processor
Reexamination Certificate
2005-08-02
2005-08-02
Chan, Eddie (Department: 2183)
Electrical computers and digital processing systems: processing
Processing architecture
Data driven or demand driven processor
Reexamination Certificate
active
06925549
ABSTRACT:
An apparatus and method for externally managing data within an asynchronous pipeline. The asynchronous pipeline over which control is sought includes a data path and a control path. In accordance with the method of the present invention, a data tag value is assigned to the data prior to its entry into the asynchronous pipeline. The data tag value is sent into the control path at the same time the data is sent into its data path such that the data tag value passes through the asynchronous pipeline in parallel with the data to which it is assigned. At a given stage within the asynchronous pipeline, the data tag value is compared with a control tag value, and only in response to the data tag value matching the control tag value is the data permitted to pass to the next stage within the asynchronous pipeline.
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Sproull et al, “The Couterflow Pipeline Processor Architecture”, Fall 1994, Design & Test of Computers, IEEE, vol.: 11, Issue: 3, pp. 48-59.
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Cook Peter William
Davies Andrew Douglas
Schuster Stanley Everett
Stasiak Daniel Lawrence
Chan Eddie
Harkness Charles
Truelson Roy W.
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