Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
2002-11-18
2003-09-09
Mai, Tan V. (Department: 2124)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
Reexamination Certificate
active
06618741
ABSTRACT:
BACKGROUND OF THE INVENTION
Execution of complex arithmetic operations and algorithms requires the continuous and repetitious use of conventional addition, subtraction, division and multiplication in ordinary binary form. All of these arithmetic operations involve addition which, as is well known, requires carry propagation that causes inefficiency each time one of these operations is used. Unfortunately, algorithm realizations utilizing conventional arithmetic generally depend on the ability to execute add and multiply operations and to use these two operations to perform the operations of subtract, divide and appropriate combinations. Conventional embedded systems using such repeated addition, subtraction, multiplication and division to achieve execution for algorithms can be extremely wasteful in terms of time and integrated circuit “real estate”.
Use of coefficient polynomial arithmetic (CPA) enables higher-level execution structures with efficient, early merging and accumulation, increasing computation volume by using the coefficient polynomials. As parallel arithmetic hardware structures, necessary to perform parallel execution, are considered for embedded computing, it is important to form at a higher level of architecture the components that are useful in executing operations and combinations of operations for application algorithms. Generally, there is potential for increased efficiency with asynchronous-logic realization when parallel or highly-parallel hardware structures are implemented at coarse-granularity levels of mathematical functionality.
The more complicated arithmetic applications demonstrate the highest efficiencies when operations and algorithms are merged creatively at routinely propitious phases of the execution process, without performing the entire basic arithmetic separately for each operation of the algorithm.
SUMMARY OF THE INVENTION
Sets of coefficient polynomials are used to design embedded-component architectures that have capability for asynchronous parallel execution at an advantageous arithmetic level where algebraic merging is realized with other operations, algorithms or applications. Factors to consider in designing such embedded-component architecture are algorithmic-hardware robustness, flexible design needs and positioning for future technology exploitation. This includes efficient-processing realizations for entire algorithms and the integration of algorithm suites. An example of the robustness of an embedded system using coefficient polynomials is illustrated in the design of an asynchronous arithmetic processor to be used as the basic design module for embedded environments.
Because of the particular hardware structures made possible by the use of CPA, higher computational granularities and complex modules are more easily feasible. Further, increased efficiency is obtained for algorithmic computations involving single and multiple operations. This is achieved by the merging of operations and the integration of algorithms, and thereby avoiding the necessity of performing the entire basic arithmetic separately for each operation or algorithm. In the Asynchronous Parallel Arithmetic (APA) Processor Utilizing Coefficient Polynomial Arithmetic (CPA)—henceforth referred to as the “APA Processor”—the sets of coefficient polynomials represent the merged operations or algorithms at much earlier time slots and their resolution to the final result level is accomplished with notably increased efficiency when compared to conventional structures.
REFERENCES:
patent: 6390980 (2002-05-01), Peterson et al.
patent: 6463163 (2002-10-01), Kresch
patent: 6480625 (2002-11-01), Yamazaki
patent: 6490364 (2002-12-01), Hanna et al.
Beam Dayn T.
Chang Hay Kyung
Mai Tan V.
The United States of America as represented by the Secretary of
Tischer Arthur H.
LandOfFree
Asynchronous parallel arithmetic processor utilizing... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Asynchronous parallel arithmetic processor utilizing..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Asynchronous parallel arithmetic processor utilizing... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3061358