Asynchronous multiple buffered communications interface having a

Details Asynchronous multiple buffered communications interface having a Asynchronous multiple buffered communications interface having a

1986-05-23

1987-07-21

Williams, Jr., Archie E.

Boots, shoes, and leggings

G06F 300, G06F 1300

Patent

active

046823042

ABSTRACT:
A communications interface for controlling asynchronous data transmission between a host computer and an input/output device achieves very high data transfer rates and reduces I/O bottlenecks. The interface includes a microprocessor and a memory addressable thereby. The microprocessor controls data transfer from the host computer into an output buffer maintained within the memory and controls subsequent data transfer from the output buffer to an output device, independently of the operation of the host computer. Data received from the host computer is stored directly into an appropriate output buffer storage location without any time-consuming reading and writing of the data by the microprocessor. This is accomplished by providing a hardware register for storing data received from the host computer. At the appropriate time data transfer from the microprocessor to the memory is disabled, and data transfer from the register to the memory is enabled. Data is thus rapidly transferred from the register directly into the memory location addressed by the microprocessor.

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patent: 4484263 (1984-11-01), Olson et al.
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