Asynchronous multi-port arbiter

Details Asynchronous multi-port arbiter Asynchronous multi-port arbiter

1981-12-21

1983-12-27

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307243, 34082551, H03K 526

Patent

active

044233841

ABSTRACT:
The arbitration circuit for granting control of a shared resource to one of a plurality of ports based upon a predetermined scheme of priority includes a plurality of input flip-flops for receiving request signals from the plurality of ports. If any of the ports have requested control, the input flip-flops are latched. A priority signal is generated indicating which of the ports has priority. This is accomplished by a second plurality of delay type flip-flops which are then latched. Additional circuitry generates a resource grant signal for transmission to a requesting port. The input flip-flops are then unlatched to permit the request signals to pass through. The second plurality of delay type flip-flops are unlatched subsequent to termination of the input request signal.

REFERENCES:
patent: 4199661 (1980-04-01), White et al.
patent: 4249093 (1981-02-01), Henig
patent: 4314164 (1982-02-01), Tin et al.
patent: 4314233 (1982-02-01), Clark
patent: 4339808 (1982-08-01), North
patent: 4375639 (1983-03-01), Johnson, Jr.
Sterling, "Modular Switch Array Includes Priority Encoder", Electronics, Aug. 1977, pp. 114-115.

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