Asynchronous multi-clock system

Details Asynchronous multi-clock system Asynchronous multi-clock system

2011-04-19

2011-04-19

Tran, Khai (Department: 2611)

Pulse or digital communications

Synchronizers

Frequency or phase control using synchronizing signal

C375S354000

Reexamination Certificate

active

07929655

ABSTRACT:
A system for controlling the transfer of a signal sequence in a first clock domain to a plurality of other clock domains. The system comprising: detecting circuitry for detecting receipt of the signals from the clock domains and setting an update signal when all of the signals received from the clock domains have a common state; and gating circuitry for receiving the update signal and operable, when the update signal is set, to allow a next signal in the sequence to be received at the input of the first circuitry.

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Sridhar, R.: “System On-Chip (SoC): Clocking and Synchronization Issues”, 17th International Conference on VLSI Design, Jan. 5, 2004, pp. 520-527, XP010679044.

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