Asynchronous modular bus architecture with cache consistency

Details Asynchronous modular bus architecture with cache consistency Asynchronous modular bus architecture with cache consistency

1994-06-10

1996-07-16

Bowler, Alyssa H.

Boots, shoes, and leggings

395800, 395285, 395446, 395451, 364DIG1, 3642408, 36424344, 36424341, 3642434, G06F 1300

Patent

active

055376401

ABSTRACT:
An asynchronous computer bus and method to maintain consistency of data contained in a cache and a memory which are each coupled to the bus. The bus comprises a cache hit indication means, a write access indication means, and a modified data indication means. A means is provided for invalidating a first portion of the cache, the invalidation means being operative upon activation of the cache hit indication means. Further, the bus comprises a modified data indication means and the write access indication means. A write-back means is provided for writing back the first portion of the cache data to the memory, the write back means being operative upon the first portion of the cache being invalidated by the invalidation means. Lastly, the bus comprises a shared data indication means which is operative on the cache hit indication means and upon failure of activation of the write access determination means.

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"Enhancing MC68030 performance using the SN74ACT2155 cache", Microprocessors and Microsystems, Vol. 14 No. 10, pp. 653-663, (Dec. 1990).
Jeong et al. "AVSLI Chip for a Multiprocessor Workstation--Part II: A Memory Management Unit and Cache Controller" 1989, IEEE.
Edenfield et al. "The 68040 on-Chip Memory Subsystem" Feb. 1990, IEEE.

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