Asynchronous interface between parallel processor nodes

Details Asynchronous interface between parallel processor nodes Asynchronous interface between parallel processor nodes

1994-09-29

1996-07-23

Safourek, Benedict V.

Multiplex communications

Wide area network

Packet switching

3701053, 370108, 375372, H04L 704

Patent

active

055397395

ABSTRACT:
An asynchronous interface enabling a processor node operating at a first clocking frequency to transfer and receive information from a communications network operating at a second clocking frequency. The asynchronous interface comprises an input synchronizer and an output synchronizer. The input synchronizer asynchronously receives a first plurality of information packets from the processor node and synchronously transfers the first plurality of information packets into the communications network. The output synchronizer, however, synchronously receives a second plurality of information packets from the communications network and asynchronously transfers the second plurality of information packets into the processor node. Both the input and output synchronizers are coupled between the communications network and the processor node.

REFERENCES:
patent: 4736465 (1988-04-01), Bobey et al.
patent: 5239544 (1993-08-01), Balzano et al.
patent: 5274680 (1993-12-01), Sorton et al.
patent: 5359600 (1994-10-01), Ueda et al.
patent: 5428609 (1995-06-01), Eng et al.

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