Asynchronous input data path technique for increasing speed...

Details Asynchronous input data path technique for increasing speed... Asynchronous input data path technique for increasing speed...

2002-11-07

2004-06-01

Lam, David (Department: 2818)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S233100, C365S189050

Reexamination Certificate

active

06744690

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates, in general, to the field of integrated circuit devices incorporating random access memory arrays. More particularly, the present invention relates to an asynchronous input data path technique of especial utility with respect to increasing speed and reducing latency in dynamic random access memory (“DRAM”) arrays and those integrated circuit devices incorporating embedded DRAM.
Many types of DRAM based devices, or integrated circuits including embedded memory arrays, are currently available including extended data out (“EDO”), synchronous DRAM (“SDRAM”), double data rate (“DDR”) DRAM and the like. Regardless of configuration, the primary purpose of the DRAM is to store data. Functionally, data may be written to the memory, read from it or periodically refreshed to maintain the integrity of the stored data. In current high density designs, each DRAM memory cell comprises a single pass transistor coupled to an associated capacitor that may be charged to store a value representative of either a logic level “1” or “0”. Data stored in these memory cells may be read out and written to them through columns of sense amplifiers coupled to complementary bit lines interconnecting rows of these cells.
A typical integrated circuit memory array architecture comprises two or more banks of memory. Generally, data to be written to the memory is input to a data interface which incorporates a full cycle latch in order to capture the data on the rising (or falling) edge of a first internal clock signal. Adjoining the edge of each bank of the memory array there is usually another, second clocked stage which receives bank address information and controls multiplexing of the data into the desired bank. Since each of the banks of the array typically comprise further sub-arrays, a third clocking stage is generally employed at the interface to each individual sub-array.
By virtue of the fact that three separate clocking stages have been employed in current designs, an overall slow write-data path results which currently requires several clock cycles in order to pipe data into the desired sub-arrays of the overall memory array.
SUMMARY OF THE INVENTION
In accordance with the technique of the present invention, by allowing the data to ripple through the sub-arrays of the memory, the speed and latency of the data-in information can be improved. A non-clocked data-in path through each bank interface allows data written to the array to ripple through to all banks all the way up to the local write (“LWRITE”) circuitry. This allows for the fastest writes possible since there are no additional clocking registers to slow down the data flow.
Particularly disclosed herein is an integrated circuit device including a memory array which comprises a plurality of memory banks forming at least a portion of the memory array. A clocked data interface receives data to be written to the memory array and is operative in response to a first clocking signal. A non-clocked bank interface is associated with each of the plurality of memory banks and at least one global data write line is in data communication between the data interface and the bank interface associated with each of the plurality of memory banks. At least one clocked sub-array interface is operative in response to a second clocking signal, and associated with each of the plurality of memory banks, with the clocked sub-array interface being in data communication with an associated non-clocked bank interface through at least one bank data write line.
Also disclosed herein is a method for supplying data to at least one global data write line in an integrated circuit device memory array. The method comprises: furnishing the data to a data interface of the memory array, allowing the data to pass through the data interface to the global data write line in response to a first state of a clocking signal and latching the data in the data interface in response to a second opposite state of the clocking signal.
Still further disclosed herein is a method for writing data to a memory array in an integrated circuit device. The method comprises: inputting data to a data interface, passing the data to at least one global data write line in response to a first state of a first clocking signal, latching the data in the data interface in response to a second state of the first clocking signal, coupling the global data write line to at least one bank data write line through a non-clocked bank interface and further coupling the bank data write line to at least one local data write line of the memory array in response to a second clocking signal.


REFERENCES:
patent: 6418077 (2002-07-01), Naven

Affiliated with

Also associated with

Rating

Asynchronous input data path technique for increasing speed... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Asynchronous input data path technique for increasing speed..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Asynchronous input data path technique for increasing speed... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3307628