Asynchronous, hierarchical loop communication system with indepe

Details Asynchronous, hierarchical loop communication system with indepe Asynchronous, hierarchical loop communication system with indepe

1975-12-22

1977-06-07

Chapnick, Melvin B.

Communications: electrical

Digital comparator systems

H04J 308, G06F 304

Patent

active

040286673

ABSTRACT:
A CPU communicates via an indirect memory access channel (IMA) to many devices on a high speed loop and an asynchronous low speed loop. The IMA connects to a loop adaptor (LAD) which connects to the primary parallel loop. A low speed serial loop is coupled to the primary loop through a general device adaptor and another LAD. The time of the loops is broken down into frames divided into inbound and outbound halves. Each half frame carries address and control data. The address in each frame is highly variable depending upon demand by devices and the allocation of service is controlled by interrupt signals by devices on the loops which can demand service whenever an empty or free inbound frame passes by their inputs as indicated by signals known as free bit signals, which are suppressed as soon as a device seizes a free inbound frame.

REFERENCES:
patent: 3544976 (1970-12-01), Collins
patent: 3633169 (1972-01-01), Bickford
patent: 3692941 (1972-09-01), Collins et al.
patent: 3731002 (1973-05-01), Pierce
patent: 3732543 (1973-05-01), Rocher et al.
patent: 3749845 (1973-07-01), Fraser
patent: 3755789 (1973-08-01), Collins
patent: 3810100 (1974-05-01), Hungerford et al.
patent: 3879710 (1975-04-01), Maxemchuk et al.

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