Asynchronous glitchless digital MUX

Multiplex communications – Wide area network – Packet switching

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

370112, 375100, H04J 300

Patent

active

052316360

ABSTRACT:
Circuit and method of glitchless switching between asynchronous data inputs to a digital multiplexer (MUX) by maintaining and conditioning the width of the clock pulse corresponding to a first data input signal so that an output pulse is produced having a pulse width that is never narrower than the narrowest of input signals, i.e., does not produce a narrow-pulse glitch. The circuit comprises select inputs in parallel to both a MUX via a select latch device and to an edge detector having an output pulse triggering a synchronization assembly. The synchronization assembly freezes the output in the last state received from the multiplexer. The select input edge detector freezes the original D0 input at a high state until the new input D1 is cleared through the synchronization assembly.

REFERENCES:
patent: 4310922 (1982-01-01), Lichtenberger et al.
patent: 4635249 (1987-01-01), Bortolini et al.
patent: 4965524 (1990-10-01), Patchen
patent: 4988901 (1991-01-01), Kamuro et al.
patent: 5099141 (1992-03-01), Utsunomiya

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Asynchronous glitchless digital MUX does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Asynchronous glitchless digital MUX, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Asynchronous glitchless digital MUX will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2347500

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.