Asynchronous FIFO increment and decrement control for...

Details Asynchronous FIFO increment and decrement control for... Asynchronous FIFO increment and decrement control for...

1999-03-30

2003-09-02

Yao, Kwang Bin (Department: 2662)

Multiplex communications

Pathfinding or routing

Store and forward

C370S395700

Reexamination Certificate

active

06614798

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to First-In-First-Out (FIFO) memory devices, and more particularly to FIFO memory devices that interface a port to a data receiving device.
BACKGROUND OF THE INVENTION
First-In-First-Out (FIFO) memory devices are widely used to store data. FIFO memory devices generally include one or more FIFO memory blocks. In a FIFO memory block, data generally is stored in sequential order as data is written into the memory block. The FIFO memory block typically is sequentially read in the same order as it was written. Thus, the data that is first written into the FIFO device is also the data that is first read from the FIFO device.
FIFO memory devices are widely used to buffer data in network applications. In network applications, data packets may be stored in the FIFO memory device in the sequential order that they are written. For routing or distribution, the data is sequentially read starting from the first data that was written.
A FIFO memory block may be used in a FIFO memory device that interfaces a port to a data receiving device. One important application of FIFO memory devices is under a specification known as the Universal Test and Operation Physical (PHY) Interface for Asynchronous Transfer Mode (ATM) specification or the UTOPIA specification. The UTOPIA specification defines an interface between one or more ports and an ATM device. In this application, the FIFO memory device synchronizes input and output of data between relatively slow physical devices and a relatively high speed ATM device.
For example, an integrated circuit FIFO memory device is marketed by Integrated Device Technology, Inc., the assignee of the present application, as Device IDT77105. See the Data Sheet entitled “
PHY
(
TC
-
PMD
)
for
25.6
and
51.2
Mbps ATM Networks”,
IDT77105, December 1998. The IDT77105 supports Asynchronous Transfer Mode (ATM) data communications and networking. The IDT77105 provides the Transmission Convergence (TC) and Physical Media Dependent (PMD) layers of a 25.6 or 51.2 Mbps physical interface suitable for ATM networks using Unshielded Twisted Pair (UTP) Category 3 (or better) wiring.
FIG. 1
is a block diagram of a conventional FIFO memory device, such as the one used in the IDT77105. As shown in
FIG. 1
, the FIFO memory device
100
includes a data input interface
102
that is coupled to an input port
106
, such as a serial port. A data output interface
104
is coupled to a data receiving device
108
, such as an ATM device. A FIFO memory block
110
is also provided. The data input interface
102
and the data output interface
104
generally operate at different clock speeds and generally operate asynchronously from one another.
Still continuing with the description of
FIG. 1
, the data input interface
102
includes a clock recovery circuit
112
that recovers a clock from a serial data signal, to generate a data signal
114
and a recovered clock
116
. A cell assembly circuit
118
assembles the data into cells and writes the cells into the FIFO
110
one byte at a time. For example, under the UTOPIA specification, cells having 53 bytes of data may be assembled. The cell assembly circuit writes data into the FIFO
110
. In
FIG. 1
, the FIFO
110
can hold three cells C
1
-C
3
, although in general, the FIFO may be configured to hold fewer or more cells. A first counter
122
counts the number of cells that are in the FIFO
110
under control of a first controller
124
. More specifically, when a cell is written into the FIFO
110
, the first controller provides an enable signal to the UP input of the first counter
122
, so that the first counter
122
increments the count. The count is also fed back to the first controller
124
.
The data output interface
104
includes a parallel output interface
130
that is responsive to data that is read from the FIFO
110
provide the data that is read from the FIFO
110
to the data receiving device
108
. A second counter
132
is provided to count the number of cells that are in the FIFO
110
. The second counter
132
is controlled by a second controller
134
. When a cell is read from the FIFO
110
, the second controller
134
provides an enable signal to the down (DN) input of the second counter
132
to decrement the count. The count is also fed back to the second controller
134
. The parallel output interface
130
, the second counter
132
and the second controller
134
are synchronized by a data output interface clock
136
that may be provided from external of the FIFO memory device
100
. As shown in
FIG. 1
, the data output interface clock
136
is independent of the recovered clock
116
.
Since the data input interface
102
and the data output interface
104
operate asynchronously, it is desirable to synchronize the first counter
122
and the second counter
132
, so that each counter accurately reflects the number of cells in the FIFO
110
, notwithstanding the different clock frequencies of the data input interface recovered clock
116
and the data output interface clock
136
. In order to provide this synchronization, a first pulse generator
150
is provided in the data input interface
102
, and a second pulse generator
160
is provided in the data output interface
104
. Upon incrementing the first counter
122
, the first controller
124
also enables the first pulse generator
150
to generate a pulse that is provided to the UP input of the second counter
132
. Thus, the second counter increments its count in response to the first pulse
152
from the first pulse generator
150
. Similarly, upon enabling the second counter
132
for decrementing by the second controller
134
, the second controller also enables the second pulse generator
160
to provide a second pulse
162
to the down (DN) input of the first counter
122
. Thus, when a cell is written into the FIFO
110
, the first pulse generator
150
causes the second counter
132
to increment. When a cell is read from the FIFO
110
, the second pulse generator
160
causes the first counter
122
to decrement.
Since the data input interface
102
and the data output interface
104
operate at different clock frequencies, and may be selectively enabled and disabled by the respective input port
106
and the data receiving device
108
, it is desirable to ensure that the first and second counters
122
and
132
are able to respond to the second pulse
162
and first pulse
152
respectively, so that an accurate count is maintained. In order to ensure that the first and second counters can respond to the pulses, a multiple cycle pulse is generally provided by the first pulse generator
150
and the second pulse generator
160
, so that the respective second counter
132
and first counter
122
can sample the pulses, and thereby increment or decrement the counter.
Unfortunately, the need to ensure that the pulses are sampled may place operating constraints on the clock frequency of the data input interface
102
and/or the data output interface
104
. The need to provide a multiple cycle pulse may also reduce the overall operational speed of the FIFO memory device
100
. Moreover, notwithstanding the provision of wide pulses, it may not be ensured that the first or second counter
122
or
124
will be active during the pulse interval. Inaccurate counts may therefore be produced.
These problems are illustrated in
FIG. 2
which is a timing diagram of operations of a FIFO memory device
100
of FIG.
1
. As shown in
FIG. 2
, the recovered clock
116
may have a predetermined frequency. The first pulse is output in synchronism with the recovered clock
116
. In order to ensure that the second counter
132
can sample the first pulse
152
, a constraint may need to be placed on the clock frequency of the data output interface clock
136
, so that it is sufficiently high frequency to ensure that the first pulse
152
is sampled. Moreover, since the data output interface
104
may be placed in an inactive mode by the data receiving device
108
, it may not be ensured that the first pulse
152

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