Asynchronous FIFO controller

Details Asynchronous FIFO controller Asynchronous FIFO controller

1996-11-18

1999-09-14

Meky, Moustafa M.

Electrical computers and digital processing systems: multicomput

Distributed data processing

365221, 36518901, 36518902, 36518906, 36523001, 36523002, G11C 700

Patent

active

059516356

ABSTRACT:
A FIFO controller circuit for interfacing data from a device running at one clock speed so that it is compatible with another device or transmission medium running at a different clock speed. A write controller is used to control the writing of data into the FIFO. The write controller is clocked at a first clock speed. A read controller is used to control the reading of data from the FIFO at a second, different clock speed. A counter is incremented when data is written to the FIFO and decremented when data is read from the FIFO. Thereby, the counter represents an amount of memory within the FIFO that is currently available. The decrement signal is generated in the first clock domain and then synchronized to the second clock domain. This provides error-free interfacing, irrespective of any phase differences existing between the two clock signals.

REFERENCES:
patent: 5347559 (1994-09-01), Hawkins et al.
patent: 5555524 (1996-09-01), Castellano
patent: 5602780 (1997-02-01), Diem et al.

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