Asynchronous FIFO buffer for synchronizing data transfers...

Details Asynchronous FIFO buffer for synchronizing data transfers... Asynchronous FIFO buffer for synchronizing data transfers...

2007-12-18

2007-12-18

Fan, Chieh M. (Department: 2611)

Pulse or digital communications

Synchronizers

C375S372000, C711S100000

Reexamination Certificate

active

10402706

ABSTRACT:
An asynchronous FIFO buffer communicates data between first and second clock domains. The FIFO buffer includes a shift register that accepts and shifts out data at a relatively high output frequency required for the second clock domain. The input data is loaded into the shift register in synchronization with the output clock; input data is not loaded into the shift register on each cycle of the output clock, however, because the input clock is slower than the output clock. A clock comparison circuit compares the input and output clocks and tracks the history of data transfers into the shift register to determine whether a given input datum should be loaded into the shift register during a given period of the output clock. The clock comparison circuit writes input datum into the shift register periodically, skipping write cycles as necessary so that input and output data rates match.

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Clifford E. Cummings; “Simulation and Synthesis Techniques for Asynchronous FIFO Design”; SNUG San Jose 2002, Rev 1.1; pp. 1-21.
U.S. Appl. No. 10/402,702, filed Mar. 28, 2003, Sabih.

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