Asynchronous event prioritizing circuit

Details Asynchronous event prioritizing circuit Asynchronous event prioritizing circuit

1980-03-04

1982-07-13

Thomas, James D.

Boots, shoes, and leggings

328108, 328154, 3408255, G06F 946

Patent

active

043398081

ABSTRACT:
A prioritizing circuit is provided for arbitrating between asynchronously occurring memory access request and memory refresh request signals to a dynamic RAM memory module. The circuit includes a latch circuit (20), a latch control circuit (21), and priority logic (22). The latch circuit is responsive to the request signals and latches the state of both signals upon receipt of a strobe signal generated by the latch control circuit. The latch control circuit generates the strobe signal upon detection of the first access request signal transmitted to the latch circuit at a predetermined logic level. To arbitrate priority between request signals occurring substantially simultaneously, the priority logic includes a combinatorial logic network responsive to the outputs of the latch circuit for generating a grant signal corresponding to the request signal having the higher priority. A delay circuit (23) provides a delayed strobe signal input to the priority logic, so that the combinatorial logic is only enabled after an appropriate settling time.

REFERENCES:
patent: 3543242 (1970-11-01), Adams, Jr.
patent: 4121285 (1978-10-01), Chen

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