Pulse or digital communications – Cable systems and components
Reexamination Certificate
1997-05-19
2001-12-04
Vo, Don N. (Department: 2631)
Pulse or digital communications
Cable systems and components
Reexamination Certificate
active
06327308
ABSTRACT:
BACKGROUND
This invention relates to asynchronous differential communication.
Asynchronous communication, where a digital signal is sent from a transmitter and collected at a receiver, one direction at a time, requires that the start and stop of each message by unambiguously delimited. In most schemes, a certain number of extra bits are added to each message to accomplish this delimiting. These extra bits use available communication bandwidth.
A variety of signaling protocols are used in asynchronous communication. Referring to
FIG. 1
, Return to Zero (RZ) signaling indicates a logical 1 by raising the signal to an upper threshold voltage level, and then falling to a lower voltage level representing a 0 state, within one clock period. Successive logical ones (10) are each separated by these returns to zero. The No Return to Zero (NRZ) protocol signals a logical 1 by raising the signal to an upper threshold voltage at the falling edge of a clock period. No Return to Zero does not separate successive logical ones (
12
) with returns to zero. The No Return to Zero Inverse (NRZI) protocol signals a logical zero by a change of state at the rising edge of a clock period. A logical one is represented by not changing the state at the rising clock edge. Thus, successive logical ones (
14
) exhibit no change of state, while successive logical zeroes (
16
a,
16
b
) indicate a change of state at each clock period.
Each of the described protocols can be sent over the same hardware-level communication line. When sending digital messages at high speeds (for example, greater than 10
6
bits per second) between relatively distant transmitters and receivers, differential signaling is preferred due to its greater noise immunity and tolerance of voltage offsets. Hardware differential signaling system
200
is illustrated in
FIGS. 2A and 2B
, where one wire
230
a
from transmitter
210
carries a V
+
signal to receiver
220
, and another wire
230
b
carries an inverse V
−
signal, and these two signals inversely mirror each other as in FIG.
2
A. Since noise and voltage drifts tend to affect both differential wires
230
a
and
230
b
similarly, their relative signal voltages tend to remain synchronized, even if their absolute voltages tend to float. The relative voltages on the two signals V
+
and V
−
define two distinct states for the differential wires: a J state, customarily defined as V
+
higher than V
−
, and a K state, defined as V
+
lower than V
−
. For Return to Zero and No Return to Zero signaling, the J state can be assigned as a logical one, and the K state can be assigned as a logical zero. For example, to implement No Return to Zero signaling, receiver
220
need only detect which of V
+
and V
−
is higher than the other at each clock period.
As a further simplification, serial asynchronous bus transmission lines in computers often use No Return to Zero Inverse (NRZI) signaling using differential signaling hardware. Since NRZI assigns logical zero to a change in signal, and logical one to no change, NRZI differential signaling requires that receiver
220
only determine whether signal V
+
has crossed signal V
−
, and not which signal wire is at a higher voltage than the other. In NRZI, any transition from state J to state K connotes a logical zero, while any persistence in either state J or state K connotes a logical one.
Data recovery of NRZI signals requires that the receiver use a clock running at a higher frequency than the data rate to oversample the state of the signal lines. Oversampling allows a certain number of data transitions to be sampled before the actual data is sent, so that the detector clock can be locked onto the periodicity of the incoming data. Once the receiver's clock is locked, the data transmission proceeds with data
0
's being transmitted by a change in the state of the signal line(s) and data
1
's being transmitted by leaving the signal lines unchanged. To maintain phase lock, the protocol must allow for some means of inserting transitions when the data comprises a long string of logical
1
's, and thus would not otherwise have transitions. Inserting transitions is often termed “bit stuffing.”
For any use of differential signaling, in any signaling protocol, some way of delimiting messages is needed. If formatting information is embedded within the data stream, the transmission medium's efficiency declines. However, if embedded formatting information is not used, the usual way to detect the end of a message is to detect that the transmitter has stopped sending. A long string of data
1
's can provide this, but the string must be longer than any string of
1
's that might occur during normal transmission.
SUMMARY
In general, in one aspect, the invention features a method for sending information on a pair of conductors that comprises sending some of the information by driving the pair of conductors in accordance with a primary signaling character set having two distinct information-carrying characters, and sending other information by driving the pair of conductors in accordance with a third distinct information-carrying character represented by a predefined state of the pair of conductors.
Implementations of the invention may include the following features. The two distinct information-carrying characters of the primary set can be represented by transition conditions of the pair of conductors. One of the distinct information-carrying characters can be represented by a change in states of the pair of conductors, and the other can be represented by no such change in states. Or, the two distinct information-carrying characters can be represented by state conditions of the pair of conductors. One of the distinct information-carrying characters of the primary set can be represented by a first predefined state of the pair of conductors, and the other information-carrying character can be represented by a second state of the pair of conductors. The first state can correspond to the first conductor being in a logical high state and the second conductor being in a logical low state, and the second state can correspond to the first conductor being in a logical low state and the second conductor being in a logical high state. Any transition from the first state to the second state and vice-versa may require temporarily driving the pair of conductors to a putative state, which can correspond to either both the first conductor and the second conductor being in a logical high state, or both the first conductor and the second conductor being in a logical low state. The third distinct information-carrying character can correspond to either both the first conductor and the second conductor being in a logical high state, or both the first conductor and the second conductor being in a logical low state, in opposite fashion to the putative state. The third distinct information-carrying character can be used to represent an end-of-message delimiter.
In general, in another aspect, the invention features apparatus for sending information on a pair of conductors that comprises a transmitter connected to the pair of conductors, the transmitter sending some of the information by driving the pair of conductors in accordance with a primary signaling character set having two distinct information-carrying characters, and a secondary driver connected to the pair of conductors, the secondary driver sending other information by driving the pair of conductors in accordance with a third distinct information-carrying character represented by a predefined state of the pair of conductors.
In general, in another aspect, the invention features apparatus for detecting information on a pair of conductors that comprises a receiver connected to the pair of conductors, the receiver detecting some of the information on the pair of conductors in accordance with a primary signaling character set having two distinct information-carrying characters, and a secondary detector connected to the pa
Compaq Computers Corporation
Conley & Rose & Tayon P.C.
Vo Don N.
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