Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2005-10-18
2005-10-18
Lam, David (Department: 2827)
Static information storage and retrieval
Addressing
Sync/clocking
C365S221000, C365S189011
Reexamination Certificate
active
06956788
ABSTRACT:
In some embodiments, a system includes a memory device in a first clock domain region and a memory device and a digital signal processing (DSP) sub-system in a second clock domain region. In addition, a plurality of asynchronous first-in first-out (FIFO) data structures, each comprising a read interface, a write interface, and one or more data slots, store data generated from the DSP sub-system. The read interface operates in the first clock domain, and the write interface operates in the second clock domain.
REFERENCES:
patent: 6525980 (2003-02-01), Au et al.
Dang Keith
Nguyen Hung
Daffer McDaniel LLP
Lam David
LSI Logic Corporation
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