Asynchronous data receiving circuit and method

Details Asynchronous data receiving circuit and method Asynchronous data receiving circuit and method

1999-12-13

2002-03-19

Le, Amanda T. (Department: 2634)

Pulse or digital communications

Receivers

Particular pulse demodulator or detector

C375S360000, C375S368000

Reexamination Certificate

active

06359943

ABSTRACT:

REFERENCE TO APPENDIX A
Appendix A, which is a part of the present disclosure, is a listing of Verilog code for an embodiment of this invention, which is described more completely below.
A portion of the disclosure of this patent document including Appendix A, contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the U.S. Patent and Trademark Office patent files or records, but otherwise reserves all copyright rights whatsoever.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to data receivers and in particular to a data receiver for communications between devices running at different clock frequencies or clock phases.
2. Description of the Related Art
In a digital electronic system, devices within the system must communicate with other devices.
FIG. 1
shows a simple digital system containing a data transmitter
110
and a data receiver
120
. Data transmitter
110
sends digital data in a data stream D to data receiver
120
over data lines
130
. In some systems, data transmitter
110
and data receiver
120
exchange control signals over control lines
140
. Data transmitter
110
and data receiver
120
can be for example, different parts of a single VLSI IC, two IC's in a system, a storage device and a computer system, two independent systems, or a digital signal processor of a CD-ROM and a CD-ROM controller chip.
If data transmitter
110
and data receiver
120
are clocked at the same phase and frequency, the transmission of data between data transmitter
110
and data receiver
120
is straight forward. However, in situations where data transmitter
110
and data receiver
120
are clocked at different phases or frequencies, data receiver
120
must capture data stream D off of data lines
130
and synchronize data stream D to the phase and frequency of data receiver
120
.
A conventional solution to capture data stream D from data line
130
to the phase and frequency of data receiver
120
is to use a dual ported FIFO (not shown) in data receiver
120
. One port of the dual ported FIFO is clocked by data transmitter
110
to store the data stream from data lines
130
. The other port of the dual ported FIFO is clocked by data receiver when data is read from the dual ported FIFO. However this solution requires a potentially expensive memory structure to be added to data receiver
120
. Furthermore, a clock signal or data write signal synchronized with data stream D from data transmitter
110
must accompany the data. Therefore, in situations where data transmitter
110
does not provide a synchronized write or clock signal to data receiver
120
, the conventional solution of using a dual ported FIFO is not feasible.
Hence there is a need for a method or apparatus to capture data from data transmitter
110
for use with data receiver
120
, when data transmitter
110
and data receiver
120
are clocked at different phases or frequencies. Furthermore, the method or apparatus should be able to capture the data even if data transmitter
110
does not provide a clock or write signal to data receiver
120
.
SUMMARY OF THE INVENTION
In accordance with this invention, a data capture circuit in a data receiver captures incoming data from a data stream at a different phase or frequency to the system clock of the data receiver. Each data word of the data stream is transmitted for a length of time called a data period. A data circuit in accordance with a first embodiment of the invention includes a signal detection circuit to detect a periodic and distinctive feature of a signal. The period between the periodic and distinctive feature of the signal is related to the data period by a scaling factor. A counter counts the number of clock periods between a first occurrence of the periodic and distinctive feature and a second occurrence of the periodic and distinctive feature. A multiplier/divider circuit multiples or divides the contents of the counter to calculate the integer clock period count, which is an approximation of the number of clock periods of the clock signal within one data period. The integer clock period count is typically stored in a count register. In some embodiments of the data capture circuit, rather than calculating the integer clock period count, the count register is programmed with the integer clock period count.
An integer N is computed from the integer clock period count, typically by dividing the integer clock period count by two in a divider. On the N-th occurrence of an active edge after the beginning of a data word, a data register captures the data word. In one embodiment of the data capture circuit, a first comparator is coupled to the divider and a counter. When the count in the counter, which is clocked by the clock signal, equals the integer N, the data register captures the data word. A second comparator is coupled to reset the counter to zero when the counter reaches the integer clock period count.
Some embodiments of the data capture circuit include an integer error compensation circuit to compensate for the error between the integer clock period count and the actual clock period count. Specifically, the integer error compensation circuit is coupled between the count register and the divider as well as between the count register and the second comparator. If the integer clock period count is greater than the actual clock period count and the cumulative error using the integer count period count is greater than or equal to half of a data period, the integer compensation circuit outputs the integer clock period count minus one. If the integer clock period count is less than the actual clock period count and the cumulative error using the integer clock period count is greater than or equal to half a data period, the integer compensation circuit outputs the integer clock period count plus one.
One embodiment of the integer error compensation circuit includes a compensation register to contain a timing error correction word, a shift register, and an adder. The timing error correction word is loaded into the shift register. On each new data word the shift register is clocked and the output bit of the shift register is added to the integer clock period count by the adder. A second embodiment of the integer compensation circuit uses a subtracter in place of or in conjunction with the adder. A third embodiment of the integer error compensation circuit replaces the compensation register with a lookup table which includes a plurality of timing error correction words. A fractional count register determines which timing error correction word is loaded into the shift register.


REFERENCES:
patent: 4298956 (1981-11-01), Rathbun et al.
patent: 5646966 (1997-07-01), Chaki et al.
patent: 5787132 (1998-07-01), Kishigami et al.

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