1997-01-24
1999-03-23
Beausoliel, Jr., Robert W.
39575001, G06F 132
Patent
active
058871292
ABSTRACT:
The present invention provides an apparatus and method for processing data, the apparatus comprising a plurality of asynchronous control circuits, each asynchronous control circuit employing a request-acknowledge control loop to control data flow within that asynchronous control circuit, and being arranged to exchange data signals with at least one other of said plurality of asynchronous control circuits. Further, a first of said asynchronous control circuits includes a halt circuit for blocking a control signal in the control loop of the first asynchronous control circuit, thereby preventing the exchange of data signals with said at least one other of said plurality of asynchronous control circuits so as to cause the control loops of said plurality of asynchronous control circuits to become blocked. The present invention is based on an asynchronous design, which only causes transitions in the circuit in response to a request to carry out useful work. It can switch instantaneously between zero power dissipation and maximum performance upon demand. According to the invention, there is provided a `Halt` circuit which causes all processor activity to cease until an interrupt occurs. The circuit preferably works by intercepting a control signal in the processing apparatus' asynchronous control circuits, effectively breaking a single request-acknowledge control loop. Since the control circuits are interrelated, blocking the response in one loop rapidly (but not instantaneously) stalls all the other control loops in the apparatus, and hence the stall ultimately propagates throughout the entire apparatus, terminating all activity. Preferably, an interrupt is used to release the stall in the original control loop, and activity then propagates from this point throughout the system.
REFERENCES:
patent: 3821709 (1974-06-01), Curley et al.
patent: 4433391 (1984-02-01), Potash
patent: 4646300 (1987-02-01), Goodman et al.
patent: 4980851 (1990-12-01), Komori et al.
patent: 5313621 (1994-05-01), Chan
Day, Paul et al., "Investigation into Micropipeline Latch Design Styles", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 3, No. 2, Jun. 1, 1995, pp. 264-272.
Day Paul
Paver Nigel Charles
Advanced Risc Machines Limited
Baderman Scott T.
Beausoliel, Jr. Robert W.
LandOfFree
Asynchronous data processing apparatus does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Asynchronous data processing apparatus, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Asynchronous data processing apparatus will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2134766