Boots – shoes – and leggings
Patent
1992-09-15
1998-01-13
Bowler, Alyssa H.
Boots, shoes, and leggings
364DIG1, 3642286, 395821, 395561, G06F 1500
Patent
active
057088306
ABSTRACT:
A coprocessor has a systolic array of processors each associated with a memory; an array data bus conveying input data to and output data from connections to the array; data buffers for the input and output data; an input and output data bus communicating with the data buffers and with a host processor; a control bus conveying successive operation codes to the array processors an instruction control store containing instructions providing operation codes for successive operations of the array processors, and a sequencer to select instructions from the control store. An intermediate data bus with a microprocessor and further random access memory communicating with that bus, carries input and output data for the array, input and output data for the microprocessor, and addresses for the memories associated with the processors of the array and for the sequencer. The control store communicates data to the intermediate bus, and the sequencer receives data from the intermediate bus, with instructions selected from the control store further providing control signals for the sequencer, the microprocessor, the intermediate bus, the further random access memory, and the input/output bus. The microprocessor generates control signals for the sequencer, and the instructions in the control store include a set of instructions for the microprocessor, so that the address sequence applied by the sequencer to the control store is modified interactively by the microprocessor responsive to instructions from the control store and data on the intermediate bus.
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Electronics Design (Advertisers Edition), Oct. 31, 1984, for NCR Corporation (Contains articles referred to in pp. 1 & 2 of specification.
Bowler Alyssa H.
Davis Jr. Walter D.
Morphometrix Inc.
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