Pulse or digital communications – Synchronizers – Frequency or phase control using synchronizing signal
Patent
1990-10-12
1995-05-30
Chin, Stephen
Pulse or digital communications
Synchronizers
Frequency or phase control using synchronizing signal
375354, 369 13, H04L 700
Patent
active
054208939
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD OF THE INVENTION
This invention relates generally to asynchronous data channels and to methods of generating and detecting asynchronous data signals in such channels. More specifically, the invention also relates to information storage subsystems of the moving medium type including such a data channel.
BACKGROUND OF THE INVENTION
In disk storage subsystems, concentric information bearing tracks on the disks are usually formatted in one of two ways. In Fixed block architecture, information is stored in fixed length Data Fields preceded by fixed length identifier (ID) fields. In Count, Key, Data (CKD) architecture, information is stored in Data fields of variable length, preceded by a Key field which identifies the following Data field and a Count field which specifies its length. In both cases the fields are separated by gaps which contain control information.
Although the data within each field is synchronous, successive fields are not guaranteed to be perfectly synchronized with each other. Accordingly, the information in the gap regions includes synchronizing information for synchronizing the circuitry which reads and/or writes the subsequent fields.
Generally, the synchronizing information is of two types known as "Bit Sync" and "Byte Sync" information. The purpose of the Bit Sync information is to synchronize a phase locked oscillator (PLO) to the bit rate of the subsequent field to allow data to be latched and decoded. The purpose of the Byte Sync field information is to synchronize a data register in a serializer/deserializer (Serdes) with byte boundaries in the subsequent fields.
One example of this prior art is the IBM 3310 Direct Access Storage which employs a disk file formatted in Fixed Block Architecture. In the disk file, the gaps preceding the ID and Data fields include a "Lead-In" field containing up to 16 bytes of logical zeroes (coded to include clock information) which is the Bit Sync information employed to synchronize clocks in the read or write circuits to the bit rate of the data in the Data fields. Following this, is a non-zero eight bit Sync Byte which decodes to binary 00000001. A ring counter used to partition the serial data in the data field into eight bit bytes synchronized with the least significant bit of the sync byte.
Because of the potential for error in decoding the single `1` bit of the Sync Byte and thus failing to synchronize with the following field correctly, more complex Sync Byte patterns have also been employed and the Sync Byte itself repeated. More complex "soft" decoding logic for such Sync Bytes can be used which is tolerant of a limited number of bits in error.
The 3310 employed relatively simple MFM (modified frequency modulation) encoding for data. More recent disk storage has employed 2, 7 RLL (Run-Length-Limited) codes in which analogous problems arise. An article by R E Jenkins entitled "2F/2F Phase Alignment System" (IBM Technical Disclosure Bulletin Vol. 23, No. 1, June 1980, p 318) shows a technique for phase aligning 1F and 2F clocks in a 2, 7 RLL channel by examining whether the bit sync information recorded over two bytes decodes correctly.
The need for byte synchronization also occurs in channels of the Partial Response Maximum Likelihood (PRML) type which are well known in the telecommunications field and have also been proposed for information storage subsystem data channels. A PRML channel for information storage applications is described in U.S. Pat. No. 4,571,734. In such channels, also known as Viterbi channels, the read back signal must be equalized to ensure it is in a standardized form for sampling. This is necessary to enable the PRML decoder to estimate the most likely digital signal sequence to have producted the sampled and digitized analog read back signal. It is known to make the equalization adaptive by including in the gaps between data fields in the signal sequence a succession of "training" bytes. Typically, the equalization pattern is a repetitive pattern with as wide a variation of frequency components as p
REFERENCES:
patent: 4791652 (1988-12-01), McEachern et al.
patent: 4928275 (1990-05-01), Moore et al.
patent: 5119406 (1992-06-01), Kramer
Anglin J. Michael
Chin Stephen
Ghebretinsae T.
International Business Machines - Corporation
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