Asynchronous clock switching between first and second clocks by

Details Asynchronous clock switching between first and second clocks by Asynchronous clock switching between first and second clocks by

1994-02-03

1996-10-08

Lee, Thomas C.

Boots, shoes, and leggings

3642705, 3642707, 3642708, 364DIG1, G06F 104

Patent

active

055640427

ABSTRACT:
A microprocessor having two on-board clock generators. The faster clock generator controls the microprocessor during normal, synchronous mode. The slower clock generator controls the microprocessor when the bus must be accessed, or during "snoop" mode which is invoked when another entry signals intent to use the bus.
A microprocessor having two on-board clock generators. The faster clock generator controls the microprocessor during normal, synchronous mode. The slower clock generator controls the microprocessor when the bus must be accessed, or during "snoop" mode which is invoked when another entity signals intent to use the bus.

REFERENCES:
patent: 4398155 (1983-08-01), Atwell, Jr. et al.
patent: 4870299 (1989-09-01), Chen
patent: 5133064 (1992-07-01), Hotta et al.
patent: 5155840 (1992-10-01), Niijima
patent: 5197126 (1993-03-01), Harrell
patent: 5231636 (1993-07-01), Rasmussen
patent: 5309561 (1994-05-01), Overhouse et al.

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