Asynchronous clock for adaptive equalization

Details Asynchronous clock for adaptive equalization Asynchronous clock for adaptive equalization

1998-02-10

2003-04-08

Corrielus, Jean (Department: 2631)

Pulse or digital communications

Receivers

Interference or noise reduction

C375S232000, C375S319000, C375S213000

Reexamination Certificate

active

06546063

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a technique for adaptive equalization.
2. Description of Prior Art
Local area network (LAN) transceivers often utilize adaptive equalization in the receivers. For example, 100Base-TX receivers typically employ this technique, in order to restore the shape of the received data pulses that are distorted due to phase shifts introduced by the cable that connects the transceivers. This is because the twisted pair wiring typically used in local area networks (LANs) can introduce severe magnitude and phase distortion in the received data. The amount of distortion depends on the cable distance, which is not known at the time of product design. For this reason, LAN transceiver products (e. g., 100Base TX, ATM and 100BaseT transceivers) frequently employ adaptive equalizers in the receiver. Unfortunately, current LAN data rates are now so high that many well-researched adaptation techniques are becoming difficult or even impossible to implement in low-cost integrated circuits (ICs), which are typically implemented in CMOS technology.
The prior art includes several basic methods for adaptive equalization. The first method assumes that sufficient statistics for controlling adaptation can be obtained from the output of relatively simple analog or digital circuits. Most commonly, in a first implementation, the output of a peak or power detector may be used to estimate cable length; that is, a low amplitude implies a long cable length, while high amplitude implies a short cable. Another common implementation compares the outputs of two or more bandpass filters, and uses that as a cable length estimator. The first of these implementations requires sampling with an analog circuit, or else with an analog-to-digital converter with sufficient precision to determine the amplitude of the received signal (e.g., 6 bit accuracy). However, even then, this first implementation is inherently inaccurate in the presence of other channel degradations, such as variable loss and transmit amplitude uncertainty. The second of these implementations is affected as well by the large variation in effective channel bandwidth that is allowed by all the recent LAN standards. Implementations that utilize analog circuitry suffer further inaccuracies due to circuit imperfections. For instance, it is difficult to implement very fast peak detectors in CMOS integrated circuit technology. Furthermore, digital implementations are degraded by quantization noise in the analog-to-digital (A/D) converter, and/or the fact that practical limitations on the amount of oversampling may make it difficult and costly to implement highly selective filters, measure rise time accurately etc. Any of these techniques requires sampling the received signal, but the resulting statistics depends on the exact point in the received pulse waveform at which a sample is taken. Therefore, meaningful measurements require either deliberate oversampling, or alternatively accurate clock recovery with both the phase and frequency being locked, typically with a phase-locked. loop.
A second method involves the use of digital signal processor (DSP) based adaptive equalizers. These equalizers have the advantage of using closed-form algorithms and well-known architectures that have been extensively studied in the literature. However, in order to converge, all these equalizers require that the receiver sampling rate eventually locks to a frequency which is (N/M)* receive baud rate, where N and M are known integers and N≧M. If N=M, then baud-rate sampling is said to be employed, and the receiver sampling clock is frequency locked to the transmitter clock. Baud-rate sampled equalizers are also notoriously sensitive to the phase of the recovered clock, and thus require the receiver to implement a complete phase-locked-loop. If N>M, then the equalizer is a fractionally-spaced equalizer, which has also been extensively analyzed in the literature. Fractionally-spaced equalizers are insensitive to phase, but do require correct frequency-locking in the receiver. Thus, these algorithms also require a recovered clock that is at least frequency locked for proper operation. Unfortunately, it may be difficult to provide for robust joint convergence of all the control loops running in a typical transceiver (clock recovery, AGC, equalizer and offset control). Furthermore, it may be inconvenient to partition the integrated circuits (IC's) involved in such a way that the recovered clock is always available to the equalizer.
A third method for adaptation monitors the output of the equalizer decision circuit for the occurrence of specific data patterns. When these patterns are deemed to have occurred, corresponding digital samples (a time domain “snapshot”) from the input to the decision circuit are then analyzed. The algorithm assumes the decisions are correct and that any deviations in the incoming waveform from an ideal waveform are due to errors in whatever parameters are being (jointly) controlled (AGC, equalizer, offset, etc.). For instance, if the equalizer were the only loop running (AGC and offset are correct), then the algorithm would assume that any deviations were due to intersymbol interference (ISI). For pulse amplitude modulation (PAM) systems, slow rise time and/or undershoot would be taken as a sign that the channel is under-equalized, while the presence of overshoot and/or ringing would presumably be because of over-equalization. The prior art has utilized algorithms which presume that the decision circuit (input to the pattern recognition block) always makes correct decisions; thus, the equalizer circuit will not converge until the sample clock is correctly phase-locked to the incoming data stream and frequency locked to M*receive baud rate, where M is a known integer ≧1. For this purpose, a phase-locked loop may be provided to obtain a clock signal that is recovered from the received pulses; i.e., a “recovered clock”.
If the equalizer sample clock is not the same as the recovered clock used for final data detection, then prior implementations of this third method have been unreliable. They are unreliable because their fine tune mechanism blindly assumes that data decisions derived from the samples input to the algorithm are mostly correct (i.e., produce a low bit error rate), and that the algorithm can in fact recognize when certain data patterns have occurred and analyze the corresponding ISI. This is despite the fact that the prior art techniques do not prevent many common scenarios which might cause the phase of the sample clock relative to the true receive data to be such that it is impossible to use the samples for reliable data recovery for indefinitely long periods of time. Thus, prior art techniques cannot guarantee that the equalizer sample clock will provide good samples (low bit error rate) for a long enough period of time within any randomly chosen acquisition window to guarantee that the equalizer will in fact converge within that window.
SUMMARY OF THE INVENTION
We have invented a equalization technique whereby a clock that has a frequency different that the incoming data frequency and not derived from the incoming pulses, referred to as an “asynchronous sampling clock”, is used to sample the incoming data. At least one comparator is used to detect data pulses, and one or more additional comparators may be activated to provide information about the data, typically including overshoot and/or undershoot. This information is used to equalize a data channel. Additional information may be obtained for AGC and DC offset compensation, if desired.


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